Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-11-19
2001-12-18
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S692000, C257S693000, C257S695000, C257S696000
Reexamination Certificate
active
06331738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device having a BGA structure and methods for manufacturing the semiconductor device, and more particularly to a semiconductor device having a BGA structure and the method for manufacturing the same, the semiconductor device being capable of preventing the generation of cracks in a solder ball with an impact propagated from a printed wiring board at the time of a fall impact test and at a time of a temperature cycle test, which tests are carried out in the state in which the semiconductor device is attached on the printed wiring board.
2. Description of the Related Art
Conventionally, there is available a semiconductor device in which a lead is used in the connection terminal.
FIG. 1
is a sectional view showing a semiconductor device in which a lead is used as the connection terminal.
As shown in
FIG. 1
, in the semiconductor device
50
, in which the lead is used as the connection terminal, there is provided a semiconductor chip
71
, and an internal leads
73
a
of a plurality of connection leads
73
are arranged in parallel with the upper surface of the semiconductor chip
71
above the semiconductor chip
71
. The semiconductor chip
71
and the internal leads
73
a
of the connection leads
73
are stuck and fixed with a sticking tape
79
comprising an insulator. Furthermore, a pad
75
formed on a central part of the upper surface of the semiconductor chip
71
and the internal leads
73
a
of the connection leads are electrically connected with wires
76
.
The semiconductor chip
71
, the sticking tape
79
, the internal leads
73
a
of the connection leads
73
, the pad
75
and the wire
76
are covered with the result that a resin sealed part
72
is formed. Furthermore, external leads
73
b
of the connection leads
73
are extended from the resin sealed part
72
and bent, and the tips of the external leads
73
b
are arranged under a lower surface of the resin sealed part
72
.
In the semiconductor device
50
which is constituted in this manner, the tips of the external leads
73
b
are fixed and connected electrically to predetermined portions of a printed wiring board with soldering or the like, and the semiconductor device
50
is set on the printed wiring board.
In the semiconductor device
50
, however, since the connection terminal is composed of the lead, it is required to prepare a solder or the like separately in advance to connect the connection terminal to the printed wiring board with the solder in the case where the connection terminal is attached on the printed wiring board. Thus, there is a disadvantage that the connection work is troublesome.
As a semiconductor device which has overcome that disadvantage, there is available a BGA (Ball Grid Array) structure. The BGA structure is constituted with a ball having a connection lead comprising solder or the like. Two kinds of semiconductor devices having the BGA structure will be explained in the forgoing description.
FIG. 2A
is a perspective view showing a semiconductor device having the BGA structure disclosed in U.S. Pat. No. 5,677,566,
FIG. 2B
is a sectional view thereof. As shown in
FIGS. 2A and 2B
, in the first conventional semiconductor device having the BGA structure
110
, there is provided a die pad
140
and a semiconductor chip
114
provided thereon. Furthermore, a plurality of connection leads
115
are electrically connected to the pad
118
formed on the end part of the upper surface of the semiconductor chip
114
with a wire
122
. Furthermore, solder balls
128
are allowed to bond on the upper surfaces of the connection leads
115
, respectively. A part of the solder ball
128
and the connection lead
115
are exposed and are covered together with the die pad
140
, the semiconductor chip
114
, the pad
118
and the wire
122
so that a resin sealed part
126
is formed.
In the first semiconductor device
110
having the BGA structure which is constituted in this manner, the solder balls
128
are allowed to come into contact with a predetermined positions of a printed wiring board. Then, by means of a reflow method for allowing the solder balls
128
to come into contact with predetermined positions of the printed wiring board and heating or pressing the solder ball
128
to melt, the semiconductor device is fixed to a predetermined position of the printed wiring board, and, at the same time, is electrically connected to the printed wiring board and is attached on the printed wiring board.
FIG. 3A
is a perspective view showing the semiconductor device having the BGA structure disclosed in the Japanese Unexamined Patent Publication No. Hei 9-213839,
FIG. 3B
is a sectional view thereof. As shown in
FIGS. 3A and 3B
, in the second conventional semiconductor device
150
having the BGA structure, there is provided a semiconductor chip
151
. Above the semiconductor chip
151
, internal leads
155
of the plurality of the connection leads are arranged in parallel with the upper surface of the semiconductor chip
151
. The semiconductor chip
151
and the internal leads
155
of the connection leads are stuck and fixed with the sticking tape
152
comprising the insulator. Furthermore, the plurality of pads
153
formed on the upper surface of the semiconductor chip
151
and the internal leads
155
of the connection leads are electrically connected with wires
154
.
Furthermore, the semiconductor chip
151
, the sticking tape
152
, the internal leads
155
of the connection leads, the pads
153
and the wires
154
are covered with an upper package member
156
comprising a sealed resin and a lower package member
157
so that the resin sealed part is formed. At positions of the surface on the side of the internal leads of the lower package member
157
which position leads to the internal lead
155
, small orifices are provided. Within the small orifices, a plurality of solder balls
158
are embedded in such a manner that each head part thereof is extended from the surface of the lower package member
157
as an external part connection terminal. This solder ball
158
is electrically connected to the internal lead
155
.
In the second conventional semiconductor device
150
having the BGA structure which is constituted in this manner, in the same manner as the first conventional semiconductor device
110
having the BGA structure, by means of the reflow method for allowing the solder balls
158
to come into contact with predetermined positions of the printed wiring board
169
and heating or pressing the solder ball
158
to melt, the semiconductor device is fixed to a predetermined position of the printed wiring board
169
, and at the same time, the semiconductor device is electrically connected and is attached on the printed wiring board
169
.
However, as has been described above, in the first conventional semiconductor device
110
having the BGA structure and the second conventional semiconductor device having the BGA structure
150
, the solder balls are embedded in the resin sealed part. As a result, an impact is propagated to the resin sealed part via the solder balls without an alleviation of the impact which is propagated from the printed wiring board at the time of the fall impact test and the temperature cycle test, which are performed in a state in which the solder balls are attached on the printed wiring board. Since the impact is applied from the resin sealed part as a the reaction force, there is a problem that a crack is generated on a bond surface with the printed wiring board in the solder ball and on a bond surface of the resin sealed part.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a BGA structure and a method for manufacturing the same, the device being capable of preventing the generation of a crack in a solder ball with a impact propagated from the printed wiring board at the time of a fall impact test and the temperature cycle test, which are performed in a state in which the sold
Clark Jhihan B
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
NEC Corporation
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