Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1998-02-11
2001-03-27
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S110000, C438S114000, C438S462000, C438S465000, C438S613000
Reexamination Certificate
active
06207477
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices having a ball grid array (BGA) contact structure and more particularly to a so-called micro-BGA device in which a circuit substrate is provided on a semiconductor chip with a size smaller than an outer dimension of the semiconductor chip.
FIG. 1
shows a conventional semiconductor device having a BGA contact structure.
Referring to
FIG. 1
, the semiconductor device includes a circuit substrate
36
and a semiconductor chip
32
provided on a top surface of the circuit substrate
36
. Further, electrodes on the semiconductor chip
32
are electrically interconnected to corresponding electrodes formed on the top surface of the circuit substrate
36
by way of a bonding wire
34
. The electrodes on the top surface of the circuit substrate
36
are in turn interconnected to respective corresponding electrodes on a bottom surface of the circuit substrate
36
via through-holes (not shown) provided in the circuit substrate
36
. The circuit substrate
36
further carries solder bumps
37
on the bottom surface in correspondence to the electrodes provided thereon. The semiconductor chip
32
on the top surface of the circuit substrate
36
is encapsulated by a resin package body
31
together with the bonding wire
34
.
FIG. 2
shows another conventional BGA semiconductor device disclosed in the U.S. Pat. No. 5,148,265.
Referring to
FIG. 2
, the BGA semiconductor device is distinct over the semiconductor device of
FIG. 1
in that a circuit substrate
46
corresponding to the circuit substrate
36
of
FIG. 1
is now provided on a top surface of a semiconductor chip
42
corresponding to the semiconductor chip
32
, with a size smaller than an outer size of the semiconductor chip
42
. Such a BGA device that uses a circuit substrate having an outer size smaller than the outer size of a semiconductor chip is called a micro-BGA device. In the micro-BGA device of
FIG. 2
, it should be noted that the solder bumps (not shown) are provided on electrodes
43
formed on the circuit substrate
46
.
In the foregoing conventional BGA device of
FIG. 1
, there arises a problem in that, because of the lateral size of the circuit substrate exceeding the size of the semiconductor chip, the overall size of the semiconductor device tends to become excessively large and a high-density mounting of the device on an electronic apparatus is difficult.
In the foregoing micro-BGA device of
FIG. 2
, on the other hand, it is necessary to bond the circuit substrate, of which size is smaller than a size of the semiconductor chip, on the semiconductor chip, while handling or alignment of such a small semiconductor chip or small circuit substrate is difficult and increases the number of fabrication steps as well as the cost of the semiconductor device.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device including a semiconductor chip and a circuit substrate, wherein the semiconductor device has an outer size substantially identical with an outer size of the semiconductor chip, and wherein the circuit substrate is attached to the semiconductor chip by a simple and easy process.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming an electronic circuit on a wafer in a region defined by a scribe line, said wafer carrying a first electrode thereon;
attaching a circuit substrate carrying thereon a predetermined conductor pattern, on said wafer, said circuit substrate carrying a second electrode and a third electrode, said step of attaching said circuit substrate including a step of aligning said circuit substrate with respect to said electronic circuit in said wafer;
interconnecting said first electrode on said wafer and second electrode of said predetermined conductor pattern by a wire bonding process;
forming a spherical electrode on said third electrode; and
dicing said wafer along said scribe line.
Another object of the present invention is to provide a semiconductor device, comprising:
a semiconductor chip having a top surface, said semiconductor chip carrying a first electrode;
a circuit substrate attached to a top surface of said semiconductor chip, said circuit substrate carrying thereon a predetermined conductor pattern including a second electrode and a third electrode;
a resin layer intervening between said top surface of said semiconductor chip and said circuit substrate;
a spherical electrode provided on said circuit substrate in correspondence to said third electrode;
a bonding wire electrically interconnecting said second electrode of said predetermined conductor pattern on said circuit substrate and said first electrode on said semiconductor chip; and
a resin potting encapsulating said bonding wire including said first and second electrodes,
said chip and said resin potting being defined by a common edge surface substantially perpendicular to a principal surface of said substrate.
Another object of the present invention is to provide a semiconductor device, comprising:
a semiconductor chip having a top surface, said semiconductor chip carrying a first electrode;
a circuit substrate attached to a top surface of said semiconductor chip, said circuit substrate carrying thereon a predetermined conductor pattern including a second electrode and a third electrode;
a spherical electrode provided on said circuit substrate in correspondence to said third electrode;
a bonding wire electrically interconnecting said second electrode of said predetermined conductor pattern on said circuit substrate and said first electrode on said semiconductor chip;
a resin potting encapsulating said bonding wire including said first and second electrodes;
a resin side wall cover covering a side wall of said circuit substrate;
said chip having a side wall substantially flush to an outer surface of said resin side wall cover, said side wall of said chip being substantially perpendicular to a principal surface of said chip.
According to the present invention, the semiconductor wafer, in which a number of semiconductor chips are formed as an integral monolithic body, is diced after the circuit substrate is attached thereto. Thereby, the adjustment for a proper positioning between the chip and the circuit substrate is achieved easily for each chip by merely conducting a positioning adjustment between the semiconductor wafer as a whole and a master circuit substrate that includes the circuit substrates with a large number in a mechanically interconnected state.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.
REFERENCES:
patent: 3855693 (1974-12-01), Umbaugh
patent: 5148265 (1992-09-01), Khandros et al.
patent: 5408127 (1995-04-01), Mostafazadeh
patent: 5814883 (1998-09-01), Sawai et al.
patent: 5858815 (1999-01-01), Heo et al.
patent: 5950070 (1999-09-01), Razon et al.
Kasai Junichi
Kawahara Toshimi
Motooka Toshiyuki
Nomoto Ryuji
Yoneda Yoshiyuki
Armstrong, Westrong, Westerman, Hattori, McLeland & Naughton, LL
Fujitsu Limited
Jr. Carl Whitehead
Vockrodt Jeff
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