Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-23
2001-05-22
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S360000, C257S364000, C257S471000
Reexamination Certificate
active
06236088
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices and, particularly, to gated semiconductor power devices and to means for protecting such devices against thermal overload conditions.
By “gated semiconductor power devices” is meant devices included within a relatively large class of devices making use of insulated gate structures in electrical power handling applications. Such class includes, but is not limited to, insulated gate bipolar transistors (IGBTs) metal-oxide-semiconductor field-effect transistors (MOSFETs) and MOS controlled thyristors (MCTs). Typically, such devices are “discrete” devices, i.e., one such device being contained within a single package, but one or more such devices can be included in power integrated circuit devices.
In general, the gate structures of such devices include, at a surface of a semiconductor substrate, a layer of metal, referred to as a gate electrode, overlying but dielectrically insulated from a channel region. The channel region is within the substrate and is disposed between source and drain regions also within the substrate. The gate electrode is electrically connected to a gate metal layer overlying the substrate but insulated therefrom for connecting the gate electrode to a terminal of the device. Similarly, the source region is electrically connected to a source region metal layer. Typically, the gate metal layer and the source region metal layer are disposed the same surface of the substrate and care is taken to avoid these metal layers from contacting one another.
In operation of such gated devices, charge carriers flow between the source and drain regions through the intervening channel region under control of a voltage signal applied to the gate electrode relative to the source region. The voltage difference between the gate electrode and the source region is a reason the gate and source metal layers are insulated from one another.
The present invention relates to the problem of thermal overloading of gated semiconductor power devices. During device operation, any number of conditions can occur in which the device is subjected to current overload while the device is in its conductive mode, i.e., the gate biased to provide a path for charge carriers through the channel region. For example, the electrical load under control of the device (e.g., a motor armature) can become shorted tending to cause the level of current flow through the device to increase sharply and the temperature of the device to rise very rapidly. Damage to the device can be avoided only if the gate bias is removed quickly enough to interrupt the current path through the channel region before the temperature of the device rises to excessive and disruptive levels.
This problem is well known and various schemes exist for protecting the semiconductor devices. Typically, such schemes make use of a temperature sensitive electrical component on the power device, e.g., a number of series connected diodes, and an electrical circuit responsive to sensed excessive temperatures for turning off the bias voltage applied to the gate electrode. Because integrated circuit technology is now well known, the electrical circuit can be included on and within the semiconductor substrate of otherwise “discrete” devices (see, for example, “Monolithic Integration of the Vertical IGBT and Intelligent Protection Circuits”, Shen and Robb, O-7803-3106-0196, 1996 IEEE, pp. 295-298.
Problems with such known schemes, however, are that they add cost and complexity to the devices being protected and are generally slow acting.
The present invention provides an exceptionally simple and fast acting protection scheme.
SUMMARY OF THE INVENTION
A semiconductor device gate structure comprises a gate electrode overlying a channel region of the device but dielectrically separated therefrom. The channel region is interposed between a source region and a drain region and controls current flow therebetween under control of a bias voltage on the gate electrode relative to the source region. The gate electrode is directly connected to a gate terminal for applying a bias voltage to the gate electrode, and the gate electrode is electrically connected to a series circuit electrically interconnecting the gate terminal to the source region. Included in the series circuit is a temperature sensitive element and an electrical resistance element.
According to one aspect of the invention, the gate electrode is included in the series circuit and comprises the resistance element. In a preferred embodiment, the gate electrode is a layer of semiconductor material doped to form a temperature sensitive semiconductor junction at an end of the gate electrode proximate to the source region and to form a distributed resistor along the gate electrode where it overlies the channel region. The gate electrode can be formed of a monocrystalline or polycrystalline semiconductor material doped to include adjoining p and n type conductivity zones forming a p-n junction therebetween. One of the zones is far more heavily doped than the other zone, and such one zone is directly connected to a metal electrode for the source region. The other zone forms the distributed resistor and is ohmically connected to the gate electrode terminal.
Alternatively, the gate electrode can be of single conductivity type and of low conductivity where it contacts the source region metal electrode for forming a Schottky barrier device.
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Burke Donald E.
Gillett Blake Andrew
Nielson John Manning Savage
Crane Sara
Intersil Corporation
Jaeckle Fleischmann & Mugel LLP
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