Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-20
2004-05-25
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S368000
Reexamination Certificate
active
06740912
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates integrated circuits generally, and particularly to a MOS transistor and its method of manufacture.
BACKGROUND OF THE INVENTION
As integrated circuit (IC) complexity increases, the size of devices within the IC must decrease. To decrease the size of a device, the various elements (features) of a device must be reduced proportionately. This is known as device scaling. One common device in integrated circuits is the metal oxide semiconductor field effect transistor (MOSFET). In a MOSFET, device scaling requires a reduction gate and channel lengths. As gate and channel lengths are reduced, a number of effects can result in unacceptable reliability and performance in the MOSFET. These effects are commonly referred to as short-channel effects and are particularly problematic in devices having channel lengths of approximately 1.25 &mgr;m or less.
One effect of the reduced channel length devices is increased horizontal and vertical electric field components, particularly in the drain region. This increase in the electric field can cause inversion-layer carriers to be accelerated (or become “hot”) to an extent that they may cause a number of harmful device phenomena, commonly referred to as hot carrier effects. Ultimately, these phenomena can adversely impact device reliability and performance.
One way to overcome hot carrier effects is through the use of a lightly doped drain (LDD) structure. In an LDD structure, the source and drain have graded doping profiles. In the source and drain regions nearest the channel, the doping level is lower, relative to the more highly doped source and drain regions farther from the channel. The lightly doped source and drain regions serve to reduce the electric field strength in the regions of the channel near the source and drain. This reduced electric field strength has been somewhat successful in reducing hot carrier generation, and thereby hot carrier effects.
While the LDD structure has been useful in reducing short channel effects such as hot carrier effects, there are certain drawbacks to its use. One such drawback is an increase in series resistance between the source and the drain (referred to as series source-drain resistance (R
sd
)). This is due to the reduced doping level at the lightly doped source and drain region. This increased resistance results in a reduction in the saturation current (also referred to as drive current I
dsat
or “on” current I
on
). A reduction in I
on
may result in a reduction in device switching speed. A MOSFET being used as a switch may be thought of as a device for charging and discharging a capacitor. The time required to charge the capacitor is directly related to the current. As such, if the current is reduced, the switching speed is reduced. Accordingly, this increase in R
sd
in conventional devices incorporating an LDD is undesireable.
Another drawback to the LDD structure is the complexity of its fabrication. In order to fabricate this structure, there are many additional processing steps that must be added to the process flow in MOSFET fabrication. These include additional photolithographic masking levels, LDD implantation and the formation of a dielectric spacer.
Accordingly, what is needed is a device that overcomes the above illustrated drawbacks of LDD MOSFET devices.
SUMMARY OF THE INVENTION
The present invention relates to a reduced feature size MOS transistor that has improved short channel effects but does not include an LDD structure. In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less.
Moreover, by eliminating the use of the LDD structure, series source-drain resistance is reduced resulting in improved drive current and switching speed.
In another embodiment, a technique for fabricating a MOS transistor is disclosed. Illustratively, a gate structure having a length of 1.25 &mgr;m or less is formed over a substrate. Thereafter, a source and a drain are formed without lightly doped regions.
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Stanley Wolf; Ph.D.; “Silicon Processing For The VLSI Era”; vol. 3; 1995; p. 234.
European Standard Search Report—Dated: Feb. 23, 2001.
Chaudhry Samir
Chetlur Sundar Srinivasan
Gregor Richard William
Roy Pradip Kumar
Sen Sidharta
Agere Systems Inc.
Warren Matthew E.
Wilson Allan R.
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