Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-02-21
2006-02-21
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S724000
Reexamination Certificate
active
07001822
ABSTRACT:
In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.
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Electronics Letters, Aug. 18, 1983, vol. 19, No. 17, pp. 684-685.
“Novel LSI/SOI Wafer Fabrication Using Device Layer Transfer Technique” by Hamaguchi et al. to IEDM 85, pp. 688-691.
Furukawa Akihiko
Inoue Yasuo
Iwamatsu Toshiaki
Maeda Shigenobu
Miyamoto Shoichi
Coleman W. David
McDermott Will & Emery LLP
Renesas Technology Corp.
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