Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-30
2001-04-03
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000, C438S479000, C438S517000, C438S157000, C438S407000, C257S347000, C257S059000, C257S063000, C257S065000, C257S066000
Reexamination Certificate
active
06210998
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an SOI (silicon on insulator) MOSFET.
2. Discussion of the Related Art
A CMOS/SOI device is used to reduce parasitic capacitance, have an abrupt slope of threshold voltage, prevent short channel effect, and remove latchup of CMOS. However, this CMOS/SOI has some problems. The most significant problem is how to prevent parasitic capacitance in a floated body NMOSFET.
As collision ionization constant of holes is very low in a PMOSEET in comparison to an NMOSEET, the problem of parasitic capacitance is not so serious as in the NMOSFET. Recently research and development has been directed to how to prevent parasitic capacitance.
A conventional semiconductor and a conventional method for fabricating the same will be described with reference to the accompanying drawings.
FIG. 1
is a cross-sectional view showing a structure of a conventional semiconductor device, including a substrate
21
in which a buried insulating layer
23
is formed, device isolating layers
27
under the surface of the substrate
21
, a gate electrode
31
a
formed on the substrate
21
of an active region between the device isolating layers
27
, and source/drain regions
35
/
35
a
formed beneath the surface of the substrate
21
at both sides of the gate electrode
31
a.
The substrate
21
is of a p type of high resistance. The source/drain regions
35
/
35
a
are of an n type that is opposite to that of the substrate
21
.
A method for fabricating the above described semiconductor substrate will be described with reference to the accompanying drawings.
FIGS. 2A
to
2
E are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
Referring initially to
FIG. 2A
, a buried insulating layer
23
is formed in a p type semiconductor substrate
21
. The buried insulating layer
23
is 100 nm thick. The active substrate
21
is 50 nm thick.
Thereafter, the substrate
21
is etched by a predetermined depth with a photo etching process to form trenches
25
.
Referring to
FIG. 2B
, an insulator is buried in the trenches so that device isolating films
27
are formed. Next, a channel ion implanting process is performed for adjusting threshold voltage.
Referring to
FIG. 2C
, a 50 Angstrom thick gate insulating film
29
is grown and a doped polysilicon layer
31
is formed. At the polysilicon layer is doped with n type impurity ions to form an NMOS device, and the polysilicon layer is doped with p type impurity ions to form a PMOS device.
Referring to
FIG. 2D
, the polysilicon layer
31
is selectively removed to form a gate electrode
31
a
and gate insulator
29
. Next, an insulating layer made of an oxide or a nitride is deposited on the entire surfaces including the gate electrode
31
a.
The insulating layer is etched-back to form sidewall spacers
33
on both sides of the gate electrode
31
a.
With the sidewall spacers
33
and the gate electrode
31
a
serving as masks, impurity ions are implanted to form source/drain regions
35
/
35
a
beneath the surface of the substrate
31
at both sides of the gate electrode
31
a.
Referring to
FIG. 2E
, the sidewall spacers
33
are removed. Next, Argon Ar ions are implanted to form damage layers
37
along impurity junction. At this time, the tilt angle for implanting the impurity ions is 4~70° and the concentration of the ions is 2×10
14
cm
2
.
R
p
is formed along the boundary of the substrate
21
and the buried insulating layer
23
due to the ion implanting process and damage layers may thus be formed by an ion implanting process.
Thereafter, an RTA (rapid thermal annealing) process is performed at a temperature of 950° C. for 10 seconds.
A recombination center is formed in a parasitic bipolar transistor body in which source, body, and drain serve as emitter, base, and collector, respectively, thereby reducing the emitter injection efficiency.
Therefore, as for an NMOS, holes generated in a body easily go toward the source which acts as the emitter, so that deterioration of the floating body effect is prevented.
The conventional semiconductor device method for fabricating the same have the following problems. Since the damage generated at the boundary of a buried insulating layer and a substrate by an Ar ion implanting process affects a gate insulating layer, the reliability of the gate insulating layer becomes poor. Also the characteristic of hot carrier becomes poor since the damage is generated at the interface of the gate insulating layer. Further, the damage region is formed in source/drain regions, and the resistance of the source/drain is increased; thus reducing the current.
SUMMARY OF THE INVENTION
therefore, the present invention is directed to an SOI MOSFET that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a semiconductor device and a method for fabricating the same in which the damage region is confined under a gate electrode to improve device performance and simplify the process.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed on a predetermined area of the substrate of an active region between gate insulating layers; sidewall spacers formed on both sides of the gate electrode to have a thickness of thicker than the gate electrode; source and drain regions formed to have LDD regions formed beneath a surface of the substrate at both sides of the gate electrode; and a damage layer formed at boundary of the buried insulating layer under the gate electrode by implanting ions.
In another aspect of the present invention, a method for fabricating a semiconductor device includes the steps of forming a buried insulating layer in a substrate; burying an insulating layer in predetermined areas of the substrate to contact with the buried insulating layer to form device isolating layers; forming a gate insulating film on the substrate and forming a gate electrode having a cap insulating film; performing an LDD ion implanting process with the gate electrtode serving as a mask and forming sidewall spacers on both sides of the gate electrode to have a thickness of thicker than the gate electrode; removing the cap insulating layer and implanting Ar ions into the entire surface to form a damage layer at a boundary of the buried insulating layer under the gate electrode; and implanting impurity ions into the substrate at both sides of the gate electrode to form source/drain regions.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 6004837 (1999-12-01), Gambino et al.
patent: 6005285 (1999-12-01), Gardner et al.
International Electron Devices Meeting 1993, Washington, D.C. Dec. 5-8, 1993, pp. 30.5.1-30.5.4.
Brock II Paul E
Hyundai Electronics Industries Co,. Ltd.
Lee Eddie C.
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