Semiconductor device for test mode setup

Details Semiconductor device for test mode setup Semiconductor device for test mode setup

1998-09-17

1999-11-09

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Testing

36523006, G11C 800

Patent

active

059826851

ABSTRACT:
A semiconductor device for a test mode setup is disclosed, which allows an SDRAM user to prevent an unwanted test mode from being set up. The semiconductor device for a test mode setup includes a command decoder for outputting a first address signal through a plurality of input signals, a shift register for outputting a second address signal, a logic part for outputting a test register setup signal by combining the first address signal with the second address signal, a test register for storing the test register setup signal, and a test decoder for outputting a test mode signal in response to the test register setup signal stored in the test register.

REFERENCES:
patent: 4860259 (1989-08-01), Tobita
patent: 5381373 (1995-01-01), Ohsawa
patent: 5781485 (1998-07-01), Lee et al.
patent: 5825782 (1998-10-01), Rodhparvar
patent: 5883843 (1999-03-01), Mii et al.
patent: 5905690 (1999-05-01), Sakurai et al.

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