Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-10-18
1995-01-17
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523006, G11C 700
Patent
active
053831560
ABSTRACT:
A dynamic random access memory includes an improved redundant use detection circuit, a redundant fuse circuit for programming a defective row, and a redundant enable circuit for enabling the redundant fuse circuit. Redundant use detection circuit includes a switching element responsive to a redundant use signal from the redundant enable circuit for conducting. High voltage is applied through an external terminal in a redundant use detection mode, and use of a redundant circuit is detected by the presence of current flowing into the redundant use detection circuit. Since a fuse element is not necessary in the redundant use detection circuit, integration density is further improved, thus permitting easy detection of use of a redundant circuit as well.
REFERENCES:
patent: 4480199 (1984-10-01), Varshney et al.
patent: 4567580 (1986-01-01), Varshney
patent: 4757474 (1988-07-01), Fukushi et al.
patent: 4862416 (1989-08-01), Takeuchi
patent: 4984205 (1991-01-01), Sugibayashi
patent: 5034925 (1991-07-01), Kato
Mitsubishi Denki & Kabushiki Kaisha
Popek Joseph A.
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