Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-18
2002-11-12
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000
Reexamination Certificate
active
06479877
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of Japanese Patent Application No. 2000-118319 filed on Apr. 19, 2000, the contents of which are incorporated herein by reference
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates a semiconductor device composed of a lateral type MOS transistor (hereinafter referred to as a main Tr) for supplying load current to a load, and a lateral type MOS transistor (hereinafter referred to as a sense Tr) connected to the main Tr in parallel for detecting current.
2. Description of the Related Art
JP-A-10-256541 discloses a load drive circuit in which a sense Tr and a main Tr for supplying load current to a load are connected to each other in parallel and constitute a current mirror circuit. Further, a voltage applied to a gate of the main Tr is controlled based on current flowing in the sense Tr and detected by a current detection resistor (sense resistor), so that a supply amount of the load current is controlled.
Referring to
FIG. 5A
, in case where each of a main Tr
101
and a sense Tr
102
is composed of lateral type MOS transistors (LDMOS device), drain cells
101
a
,
102
a
and source cells
101
b
,
102
b
of the main Tr
101
and the sense Tr
102
are arranged in a mesh shape (lattice arrangement) on an identical substrate. Further, as shown in
FIG. 5B
, the main Tr
101
and the sense Tr
102
respectively have source wiring members
103
for connecting the source cells
101
b
,
102
b
and drain wiring members
104
for connecting the drain cells
101
a
,
102
a
. Each of the source wiring members
103
and the drain wiring members
104
is formed into a comb shape so as to prevent short circuit from occurring among the source cells
101
b
,
102
b
, and the drain cells
101
a
,
102
a.
When currents are applied to the LDMOS devices, however, there arises a difference in calorific value or heat release between the main Tr and the sense Tr, and temperature distribution occurs on the chip surface where the LDMOS devices are formed. Also when the chip is packaged, because stress derived from a package varies with positions, the stresses imparted to the main Tr and the sense Tr vary and become different from each other. This results in variations in ON resistance of the main Tr and the sense Tr and a shifted current mirror ratio. In consequence, the above-described load drive circuit cannot control the current accurately.
Especially when the main Tr
101
and the sense Tr
102
are formed on an SOI substrate, the main Tr
101
and the sense Tr
102
are formed at respective regions that are isolated from each other by a trench. In this case, problems caused due to thermal effects become prominent.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above problems. An object of the present invention is to provide a semiconductor device capable of performing a current control by a load drive circuit at a high accuracy.
According to the present invention, a semiconductor device has a main MOS transistor formed on a substrate for supplying a current to a load, and a sense MOS transistor connected to the main MOS transistor in parallel to form a current mirror circuit with the main MOS transistor for controlling the current supplied to the load. Each of the main MOS transistor and the sense MOS transistor is composed of a lateral type MOS transistor and forms a current path in a direction parallel to a surface of the substrate. The sense MOS transistor is incorporated in the main MOS transistor and forms a polygonal shape on the surface of the substrate in cooperation with the main MOS transistor. Further, the sense MOS transistor extends to pass through a corner and a center of the polygonal shape.
According to the semiconductor device as described above, variations in ON resistance of the main MOS transistor and the sense MOS transistor can be prevented, and a shift of a current mirror ratio can also be prevented. In consequence, the current that is to be supplied to the load can be controlled accurately.
REFERENCES:
patent: 4636825 (1987-01-01), Baynes
patent: 5408141 (1995-04-01), Devore et al.
patent: 5412239 (1995-05-01), Williams
patent: 5530277 (1996-06-01), Otsuki et al.
patent: 5672894 (1997-09-01), Maeda et al.
patent: 5780904 (1998-07-01), Konishi et al.
patent: 5999041 (1999-12-01), Nagata et al.
patent: 6011413 (2000-01-01), Hayakawa et al.
patent: 10-256541 (1998-09-01), None
US 6,104,076, 8/2000, Nakayama et al. (withdrawn)
Wolf, “Silicon Processing for the VLSI Era, vol. 2-Process Integration,” 1990, Lattice Press, vol. 2, pp. 66-67.
Fujimoto Hiroshi
Koyama Yoshiki
Ueda Nobumesa
Denso Corporation
Flynn Nathan J.
Law Offices of David G. Posz
Quinto Kevin
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