Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-24
2004-06-15
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S409000
Reexamination Certificate
active
06750513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More specifically, the invention relates to an insulated-gate field-effect transistor and a bipolar transistor, both formed on an SOI substrate.
In a high breakdown voltage semiconductor device formed on the SOI (Silicon On Insulator) substrate, the magnitude of the breakdown voltage of the device determines the thickness of a silicon layer and the thickness of a buried insulating film. The silicon layer is the active region where the device is formed, and is formed over a support silicon substrate via the insulating film. The breakdown voltage of an N-channel insulated-gate field-effect transistor is herein defined as a voltage applied to a drain electrode therein when an electric current flowing through the drain electrode has become 10 &mgr;A through the application of the voltage to the drain electrode. In this case, the gate width of the field-effect transistor measured with an IWATSU semiconductor curve tracer TT-508 is 50 &mgr;m, and source and gate electrodes and the back of the SOI substrate where the device is formed are set at the ground level or 0 V. Alternatively, the breakdown voltage of a P-channel insulated-gate field-effect transistor is herein defined as a voltage applied to a source electrode or a gate electrode therein when a current flowing through the source electrode has become 10 &mgr;A through the application of voltages applied to both the source and gate electrodes. In this case, the gate width of the field-effect transistor measured with the above-mentioned curve tracer is 50 &mgr;A, and a drain electrode and the back of an SOI substrate is set at the ground level (0 V). Alternatively, the breakdown voltage of an NPN bipolar transistor is herein defined as a voltage applied to a collector electrode therein, or BVceo when a current flowing through the collector electrode has become 10 &mgr;A through the application of the voltage to the collector electrode. The emitter length of the bipolar transistor measured with the curve tracer is 50 &mgr;m in this case, and the base electrode is set to open, and an emitter electrode and the back of an SOI substrate are set at the ground level. Still alternatively, the breakdown voltage of a PNP bipolar transistor is herein defined as a voltage applied to an emitter electrode therein when a current flowing through the emitter electrode has become 10 &mgr;A through the application of the voltage applied to the emitter electrode. In this case, a collector electrode and the back of an SOI substrate is set at the ground level and a base electrode is set to open by the use of the above-mentioned curve tracer.
The thicker the silicon layer and the thicker the buried insulating film, a device with an increased breakdown voltage can be fabricated. However, when the buried insulating film becomes thick, a warp in a wafer increases in the manufacturing process of the device. Consequently, the process at the final stage in completion of the device cannot be performed. Further, the larger a wafer diameter, the more manifest this phenomenon becomes. In general, in the wafer with a diameter of 6, 8, or 12 inches, a silicon oxide film is now commonly employed as the buried insulating film. The maximum thickness of the buried insulating film is regarded as approximately 3 &mgr;m. For this reason, when a high breakdown voltage device is fabricated, it is necessary to increase the thickness of the silicon layer, which is the active region. However, if the thickness of the silicon layer is increased, it takes much time to form trenches required for isolation of a device-forming region. For this reason, throughput is reduced, so that a cost problem arises. In addition, it becomes difficult to form a completely vertical deep trench and cover the trench with an insulated film tightly.
FIGS. 2A and 2B
show the structure of a high breakdown voltage N-channel MOS field-effect transistor and the structure of a high breakdown voltage NPN bipolar transistor, both using an SOI substrate with an N-type device-forming region and having a breakdown voltage of approximately 200 to 600 V, respectively.
FIG. 2A
illustrates the N-channel MOS field-effect transistor formed on an SOI substrate
101
having an N-type region over a buried insulating film
103
. The transistor comprises a high concentration N-type layer
402
and a high concentration p-type layer
401
both contacting a source electrode
201
, a gate insulating film
301
and a gate electrode
302
, a high concentration N-type layer
403
, and a p-type semiconductor layer or a p-body layer
404
. The gate insulating film
301
and the gate electrode
302
are in contact with the high concentration N-type layer
402
. The high concentration N-type layer
403
is in contact with a drain
202
disposed in a lateral direction via a field oxide film
204
contacting the gate electrode. The p-body layer
404
is in contact with the gate oxide film, and the high concentration N-type and P-type layers contacting the source electrode. As a drain region interposed between the p-body layer and the drain electrode, the N-type substrate is usually employed without alteration. Alternatively the concentration of the drain region may be adjusted by ion implantation and diffusion of phosphorus ions, for example. An n-type layer formed by implantation and diffusion of ions of an element such as phosphorus into the substrate is hereinafter referred to as a WELL and the concentration of the resulting layer is referred to as a WELL concentration.
FIG. 2B
illustrates the NPN bipolar transistor formed on the SOI substrate
101
having the N-type region over the buried insulating film
103
. The transistor comprises a collector electrode
205
, an emitter electrode
207
and a base electrode
206
disposed via the field oxide film
204
, high-concentration N-type layers
411
and
413
, a high concentration P-type layer
412
, and a P-type base region
414
. The high-concentration N-type layer
411
is in contact with the collector electrode. The high concentration N-type layer
413
is in contact with the emitter electrode
207
. The high concentration P-type layer
412
is in contact with the base electrode. The p-type base region
414
is in contact with the high concentration N-type layer contacting the emitter electrode and the high concentration P-type layer contacting the base electrode. As a collector region interposed between the p-type base region and the collector electrode, the n-type substrate is usually employed without alteration, or the WELL is formed for use as the collector region. The NPN bipolar transistor is usually what is called a vertical structure with a high concentration N-type layer brought into contact with the buried insulation film. However, the present invention has been made to reduce the thickness of the silicon layer. Accordingly, if the high concentration N-type layer is present in the silicon layer with its thickness reduced, a high breakdown voltage cannot be obtained. Thus, a lateral structure in which the high concentration N-type layer contacting the buried insulating film has been solely removed from the conventional vertical structure is herein defined as a conventional structure.
Now, a mechanism whereby a breakdown voltage is determined will be described. In the case of the N-channel MOS field-effect transistor illustrated in
FIG. 2A
, when a voltage is applied to the drain electrode, a depletion layer formed between the p-body layer and the N-type substrate is extending. In addition, a depletion layer is extending from the vicinity of the buried insulating film under the drain electrode as well. If a drain-source distance is short, a rise in the electric field of the depletion layer formed between the p-body layer and the N-type substrate becomes faster than a rise in the electric field of the depletion layer formed in the vicinity of the buried insulating film. If the drain-source distance becomes long, the depletion laye
Ohyanagi Takasumi
Watanabe Atsuo
Hitachi , Ltd.
Wilson Allan R.
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