Semiconductor device fabrication method using an interface...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S643000, C438S687000, C438S680000

Reexamination Certificate

active

06358829

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having a metal interconnection layer connected to a lower conductive layer via a fine contact.
2. Description of the Related Art
Higher levels of integration in semiconductor devices have lead to contact holes having smaller diameters and higher aspect ratios. Accordingly, technologies that can effectively fill such fine contact holes have been suggested. A conventional physical vapor deposition (PVD) produces a layer having poor step coverage and thus does not completely fill a fine contact hole. As an alternative, chemical vapor deposition (CVD) can fill a contact hole with tungsten (W), forming a tungsten plug. However, tungsten plugs have high resistivity and increase contact resistance. Contact resistance increases further when a tungsten plug reacts with an aluminum (Al) interconnection layer formed thereon. Blanket deposition of aluminum provides a relatively low resistivity material that does not react with aluminum interconnect layers. However, as the thickness of a CVD deposited Al layer increases, the surface morphology of the Al layer becomes more irregular which makes filling of contact holes difficult.
SUMMARY OF THE INVENTION
In accordance with an aspect of the present invention, a fabrication process forms an interface control layer before a blanket deposit of a conductive layer of aluminum or a similar material. The interface control layer is a thin layer typically including multiple atomic layers. The interface control layer provides uniformly and densely distributed nucleation sites from which the conductive layer grows uniformly. Accordingly, the fabrication process forms a smooth-surfaced aluminum layer that can fill fine contact holes.
In accordance with one embodiment of the present invention, a semiconductor device includes an interlayer dielectric (ILD) film having a contact hole on a semiconductor substrate. The contact hole exposes a conductive region of the semiconductor substrate. The fabrication method forms an interface control layer having multiple atomic layers deposited on an inner wall of the contact hole and an upper surface of the interlayer dielectric film and then deposits Al on the interface control layer by a chemical vapor deposition (CVD) to form both a contact plug in the contact hole and an interconnection layer connected to the contact plug. Between forming the interface control layer but after forming the ILD film, an ohmic layer can be formed on the exposed conductive region of the semiconductor substrate, the side wall of the contact hole in the interlayer dielectric film, and the upper surface of the interlayer dielectric film; and a barrier layer such as a Ti-rich TiN layer can be formed on the ohmic layer.
An atomic layer deposition (ALD), cyclic CVD or digital CVD can form the interface control layer by depositing a single metal or an alloy film. For example, the interface control layer can be a thin aluminum (Al) film containing silicon (Si). To form such interface control layer, a flow of Si-containing gas is applied a structure including the barrier layer, to adsorb Si to the surface of the barrier layer, and then excess Si-containing gas is removed from around the structure. Applying an Al-containing gas to the resultant structure adsorbs Al to the surface of the barrier layer and to the adsorbed Si. Then, excess Al-containing gas is removed from around the structure, and these steps are repeated to form on the barrier layer a thin Al film containing Si. During the Al adsorption, hydrogen (H
2
) gas may be supplied together with the Al-containing gas to facilitate deposition of Al.
Forming the contact plug and the interconnection layer can be performed in-situ, in the same processing device or chamber in which the interface control layer is formed.
The fabrication method can further include adsorbing hydrogen or nitrogen to the surface of the interface control layer to form a surface treatment layer on the interface control layer, before forming the contact plug and the interconnection layer. The surface treatment layer prevents oxidation of the interface control layer and maintains the desired density and uniformity of nucleation sites.
In addition to the above steps, fabrication methods in accordance with other embodiments of the invention can include annealing after depositing the Al interconnection layer on the interface control layer. The annealing forms an interconnection layer doped by a diffusion of atoms from the interface control layer into the interconnection layer. In the method, the interface control layer is typically copper (Cu), titanium (Ti), tungsten (W), silicon (Si), tantalum (Ta) or silver (Ag).
When the interface control layer contains copper, a source gas such as (hexafluoroacetyl)copper(trimethylvinylsilane) [(hfac)Cu(TMVS)], CuCl
2
, Cu
2
I
4
, or a combination thereof is applied to adsorb Cu to the surface of the barrier layer. To form multiple atomic layers, the chamber containing the resultant structure is purged using a purging gas, and then applying the copper containing gas and purging are repeated. Annealing for diffusion of copper is typically performed at 300 to 650° C.
When the interface control layer is formed of Ti, a gas such as TiCl
4
, tridiethylamine titanate (TDEAT), tridimethylamine titanate (TDMAT), or a combination thereof is flushed across the surface to adsorb Ti.
When the interface control layer is formed of W, the flushing is performed with WF
6
gas.
When the interface control layer is formed of Si, a gas such as SiH
4
, SiH
3
Cl, SiHCl
3
, Si
2
H
6
, SiCl
4
or a combination thereof is flushed. Here, annealing may be performed at 400 to 650° C.
Another method for fabricating a semiconductor device includes forming an interlayer dielectric (ILD) film having a contact hole that exposes a conductive region of a semiconductor substrate. A first interface control layer as a thin Al film containing Si is formed on the inner wall of the contact hole and the upper surface of the interlayer dielectric film, to a thickness on the order of several angstroms to several tens of angstroms. Then, a second interface control layer having a plurality of atomic layers of a material such as Cu is formed on the first interface control layer, and an Al blanket deposition is performed on the resultant structure by chemical vapor deposition (CVD), to form a conductive layer filling the contact hole and simultaneously covering the upper surface of the interlayer dielectric film. Annealing the resultant structure forms an Al interconnection layer doped with Si and Cu.
Between forming the first interface control layer and forming the ILD film, an ohmic layer can be formed on the exposed conductive region of the substrate, the side wall of the interlayer dielectric film in the contact hole, and the upper surface of the interlayer dielectric film, and then a barrier layer is formed on the ohmic layer. The first interface control layer is formed on the barrier layer.
Atomic layer deposition (ALD), cyclic CVD or digital CVD can form the first and second interface control layers, and the first interface control layer, the second interface control layer and the conductive layer can be formed successively formed in-situ in the same deposition chamber. In one embodiment, between forming the conductive layer and forming the second interface control layer, a surface treatment layer on the second interface control layer is formed to prevent oxidation of the surface of the second interface control layer.
According to an aspect of the present invention, a semiconductor device fabrication method forms an Al interconnection layer having excellent surface morphology and thereby improves reliability of the interconnection layer.


REFERENCES:
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5552341 (1996-09-01), Lee

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