Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-28
2001-08-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S257000, C438S264000
Reexamination Certificate
active
06277734
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device fabrication method, more specifically a semiconductor device fabrication method which can micronize lines.
As LSI becomes larger-scaled, device micronization is pursued.
In order to realize semiconductor integrated circuits including gate electrodes, lines and contact holes of microdimensions it has been conventionally conducted that the lithography uses short exposure wavelengths for higher resolving ability.
While minimum development dimensions are thus diminished, various device structures which allow alignment margins for alignment between lithography steps have been studied so as to make dimensions of devices smaller without diminishing dimensions of patterns to be formed.
Self-aligned contact (hereinafter called SAC) is noted as a technique that can reduce dimensions of devices without diminishing dimensions of patterns to be formed.
In semiconductor device fabrication methods using SAC, when an inter-layer insulation film
130
is etched, as shown in
FIG. 7A
, a stopper film
128
functions as the etching stopper, and protects an insulation film
118
from excessive etching, whereby a gate electrode
120
can be prevented from exposure. Even if a disalignment takes place in a lithography step, a contact hole
132
can be formed at a preset position.
However, in the above-described semiconductor device fabrication method, as a pitch between gate electrodes
120
becomes smaller with more micronization of the semiconductor device, as shown in
FIG. 7B
a stopper film
128
unpreferably defines a small gap
129
. As a result, when the inter-layer insulation film
130
is etched with the stopper film
128
as the etching stopper, sometimes that of the inter-layer insulation film
130
in the gap
129
cannot be completely removed.
In such case, in order to remove all the inter-layer insulation film
130
in the gap
129
, overetching must be performed. However, the overetching often unpreferably etches not only the inter-layer insulation film
130
but also the stopper film
128
and the insulation film
118
, and often unpreferably exposes even the gate electrodes
120
or etches even the silicon substrate
110
. This often degrades reliability of the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device fabrication method which can micronize the semiconductor device without degrading reliability thereof.
The above-described object is achieved by a semiconductor device fabrication method comprising the steps of: forming on a substrate a plurality of lines on upper surfaces and side surfaces of which a first insulation film is formed on; depositing a second insulation film on and/or above the substrate and said lines, filling gaps between one of said lines and its adjacent one to thereby form the second insulation film; forming on the second insulation film a third insulation film having etching characteristics different from those of the second insulation film; etching the third insulation film with the second insulation film as a stopper; and etching the second insulation film to form a contact hole which reaches the substrate. The second insulation film is deposited substantially perpendicular to the substrate, whereby the surface of the second insulation film defines no narrow gap, and a required contact hole can be formed. A semiconductor device can be fabricated without degrading its reliability.
The above-described object is achieved by a semiconductor device fabrication method comprising the steps of: forming on a substrate a plurality of lines on upper surfaces and side surfaces of which a first insulation film is formed; forming a second insulation film on the substrate and said lines, filling gaps between one of said lines and its adjacent one; forming on the second insulation film a third insulation film having etching characteristics different from those of the second insulation film; etching the third insulation film with the second insulation film as a stopper, and further etching the second insulation film to form a contact hole which reaches the substrate; and forming a fourth insulation film in the contact hole. Even in a case that a large undercut is formed in the second insulation film, an insulation voltage resistance can be high between adjacent contact holes. Accordingly, a micronized semiconductor device can be fabricated without degrading its reliability.
REFERENCES:
patent: 5841195 (1998-11-01), Lin et al.
patent: 5847463 (1998-12-01), Trivedi et al.
patent: 5920098 (1999-07-01), Liaw
patent: 6037223 (2000-03-01), Su et al.
patent: 4-29327 (1992-01-01), None
patent: 4-359521 (1992-12-01), None
patent: 5-13434 (1993-01-01), None
patent: 6-61253 (1994-03-01), None
patent: 6-196498 (1994-07-01), None
patent: 6-196499 (1994-07-01), None
patent: 6-260497 (1994-09-01), None
patent: 8-162635 (1996-06-01), None
patent: 8-264770 (1996-10-01), None
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Le Dung A
Nelms David
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