Semiconductor device fabricating method

Details Semiconductor device fabricating method Semiconductor device fabricating method

2002-12-03

2004-04-20

Norton, Nadine G. (Department: 1765)

Abrasive tool making process, material, or composition

With inorganic material

Clay, silica, or silicate

C438S691000, C438S693000

Reexamination Certificate

active

06723144

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a polishing techniques for the planarization of a surface of a wafer and, more specifically, to a semiconductor device fabricating method which planarizes a thin film formed on a semiconductor wafer by polishing.
The number of components per semiconductor IC (integrated circuit) device has progressively increased in recent years and the component elements of semiconductor IC devices have been miniaturized accordingly. When forming those elements of a semiconductor IC device, films need to be patterned by lithography techniques. Light of a short wavelength and an optical element having a large numerical aperture must be used to form a minute pattern, which, however, involves reduction in the focal depth of the optical element. A semiconductor device fabricating method comprises many pattern forming processes. A metallization process will be described with reference to
FIGS. 2A
to
2
F by way of example.
FIG. 2A
is a sectional view of a semiconductor wafer
1
of silicon provided with a first interconnection layer
3
of aluminum thereon. A insulating film
2
is formed on a surface of the wafer
1
so as to cover transistors formed on the wafer
1
. The first interconnection layer
3
is formed on the first insulating film
2
. Parts
3
′ of the first interconnection layer
3
corresponding to holes formed in the insulating film
2
are recessed. An interlayer dielectric film
4
, i.e., a silicon dioxide film inmost cases, and a second wiring line
5
of aluminum are formed on the first interconnection layer
3
. A photoresist is applied to the second interconnection layer
5
to form a photoresist film
6
to be used for patterning the second interconnection layer
5
as shown in FIG.
2
B.
Subsequently, as shown in
FIG. 2C
, the photoresist film
6
is exposed to light by a stepper
7
provided with a photomask and a demagnification projection lens to form an image of a circuit pattern formed on the photomask. If the stepper
7
has a small focal depth, the image of the circuit pattern cannot be focused properly on both recessed parts and projecting parts
8
of the photoresist film
6
and the image cannot be formed in a satisfactory resolution. Generally, the surface of the wafer
1
provided with the transistors is irregular, the stepper
7
must have a great focal depth.
The surface of the interlayer dielectric film
4
is subjected to a planarizing process to solve the foregoing problems. As shown in
FIG. 2D
, the interlayer dielectric film
4
is formed on the first interconnection layer
3
formed as shown in FIG.
2
A. Portions of the interlayer dielectric film
4
projecting from a level
9
below the bottoms of the recessed parts of the interlayer dielectric film
4
are removed by the planarizing process using a chemical mechanical polishing method (hereinafter referred to as “CMP method”) to planarize the surface of the interlayer dielectric film
4
as shown in FIG.
2
E. Then, the second interconnection layer
5
of aluminum and the photoresist film
6
are formed to be exposed to light by the stepper
7
. Since the surface of the photoresist film
6
thus formed is flat, the image of the circuit pattern can be formed in a satisfactory resolution even if the focal depth of the stepper
7
is small.
The CMP method is disclosed in U.S. Pat. No. 4,944,836 and Japanese Examined Patent Publication No. Hei 5-30052.
FIG. 3
is a typical view of a CMP device illustrating the conception of the CMP method. As shown in
FIG. 3
, a circular polishing pad
11
is stuck on a turntable
12
. The turntable
12
is rotated, for example, in a counterclockwise direction. The polishing pad
11
is, for example, a thin sheet of foam urethane resin formed by slicing a foam urethane resin block. Polishing pads respectively having different qualities and different degrees of minuteness in surface structure are used selectively according to the type of workpieces and desired surface roughness in which the surfaces of workpieces are to be finished. The wafer
1
is fixed to an elastic backing pad
13
fixed to a wafer holder
14
. The wafer holder
14
is rotated in the same direction as the turntable
12
, the wafer
1
is pressed against the surface of the polishing pad
11
, and a polishing slurry
15
containing abrasive powder is supplied onto the polishing pad
11
to planarize the surface of the wafer
1
by polishing.
When polishing an insulating film of silicon dioxide or the like, high-purity silica (fumed silica) powder is used for polishing. The grain size of the silica powder is in the range of about 30 to about 150 nm. The polishing slurry
15
is prepared by suspending silica particles in an alkaline solution, such as a potassium hydroxide solution or an ammonia solution. The polishing slurry
15
is able to finish the surface of the wafer
1
in a flat, smooth surface not damaged significantly.
Another planarizing technique uses a fixed abrasive tool instead of the polishing slurry. A polishing device employed in executing the planarizing technique using the fixed abrasive tool has the same construction as the polishing device employed in the CMP technique, except that the former uses a fixed abrasive tool instead of the polishing pad. The fixed abrasive tool is attached to a platen, and deionized water is supplied instead of the abrasive slurry onto the fixed abrasive tool. This planarizing technique employing the fixed abrasive tool is disclosed in PCT International Publication No. WO 97/10613 and Japanese Patent Laid-open No. Hei 8-216023.
Pattern size dependence is a generally used quantitative index of macroscopic planarizing ability. When a wafer provided with a large pattern and a small pattern is subjected to polishing, the small pattern is polished at a polishing rate higher than that at which the large pattern is polished. When a large pattern and a small pattern are polished by a polishing process having a low planarizing ability, the difference in abraded amount between the large pattern and the small pattern is large. More concretely, pattern size dependence can be determined by polishing a pattern having some isolated lines having a height of about 0.8 &mgr;m and widths in the range of about 0.1 &mgr;m to about 5 mm, and spaces between the lines formed on a test wafer as shown in
FIG. 8
, and measuring the differences between the amounts of abraded portions of the isolated lines. When narrows lines of widths less than 1 mm and wide lines of widths not smaller than 3 mm are polished by using a standard polishing pad and a standard polishing slurry, the height of the wide lines is 0.38 &mgr;m or above when the narrow lines are abraded completely, and the wide lines cannot completely be abraded even if the polishing process is continued further.
As mentioned above, it is difficult to planarize completely a layer formed over a pattern and having steps corresponding to the pattern by the conventional CMP process. However, a memory mat of an actual 64 Mbit DRAM (dynamic random-access memory) has 8 to 10 mm sq. pattern elements of about 0.8 &mgr;m in height.
The foregoing planarizing process employing the fixed abrasive tool has an excellent ability to planarize pattern elements including large ones. The planarizing process employing the fixed abrasive tool is characterized by its very high planarizing ability. For example, as obvious from
FIG. 8
, whereas the CMP process planarizes a 3 mm wide pattern element to a height of 0.38 &mgr;m (380 nm), the planarizing process using the fixed abrasive tool is able to planarize the same pattern element to a height of 18 nm, which is extraordinarily small as compared with 380 nm.
The planarizing process employing the fixed abrasive tool is able to planarize pattern elements of large sizes of several millimeters or above which cannot satisfactorily be planarized by the CMP process because the abrasive grains of the fixed abrasive tool are fixed and the fixed abrasive tool has a high elastic modulus. Furthermore, since the fixed abrasive tool is scarc

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