Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Patent
1996-08-23
2000-12-05
Crane, Sara
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
257528, 257532, 257536, H01L 2358
Patent
active
061570451
ABSTRACT:
An evaluation pattern and an evaluation method of devices capable of measuring with precision the unit capacitance and specific precision of passive devices necessary in analog circuits on a single semiconductor substrate, unit capacitors in such a quantity to overcome the measuring error of measuring instruments, arranged in an array by nx pieces in the X direction (nx being a natural number) and ny pieces in the Y direction (ny being a natural number), are connected by wiring to be capable of measuring the sum of capacitances in each column at least in one of the array directions in the X and Y directions of the unit capacitors.
REFERENCES:
patent: 4573058 (1986-02-01), Brooks
patent: 4969124 (1990-11-01), Luich et al.
patent: 5057451 (1991-10-01), McCollum
patent: 5341049 (1994-08-01), Shimizu et al.
patent: 5429979 (1995-07-01), Lee et al.
patent: 5536968 (1996-07-01), Crafts et al.
patent: 5625220 (1997-04-01), Liu et al.
Strait, P.T., A First Course in Probability and Statistics with Applications, Harcourt Brace Johanovich, pp. 443-452, 1983.
Patent Abstracts of Japan, Publication No. 02003945 published Jan. 1990.
Crane Sara
Matsushita Electric - Industrial Co., Ltd.
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