Semiconductor device evaluation method, method of controlling th

Details Semiconductor device evaluation method, method of controlling th Semiconductor device evaluation method, method of controlling th

1998-07-23

2000-06-20

Picardat, Kevin M.

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 14, 438 18, G01R 3126, H01L 2100

Patent

active

060777192

ABSTRACT:
An electric field changing in the form of a ramp waveform with the passage of time is applied to an oxide layer, and the electric current densities applied to the oxide layer at measuring points of time are measured. The electric current densities applied until the oxide layer is broken down, are integrated with respect to time, thus obtaining a total electric charge amount Qbd used up to the breakdown of the oxide layer. The total electric charge amount Qbd is divided by each of the electric current densities at the measuring points of time, thus obtaining each of the estimated values of oxide layer lifetime at the time when it is supposed that each of the electric current densities at the points of time was constantly applied. Using the field intensities and the lifetime estimated values at the common measuring points of time, there is determined a regression line in which the oxide layer lifetime estimated values are expressed in the form of a function of the field intensities. Based on the regression line, a field acceleration coefficient is determined and the oxide layer lifetime at an optional field intensity is estimated.

REFERENCES:
patent: 5449638 (1995-09-01), Hong et al.
patent: 5686346 (1997-11-01), Duane
patent: 5773989 (1998-06-01), Edelman et al.
A. Berman, "Time-Zero Dielectric Reliability Test by a Ramp Method", IEEE/PROC. IRPS, pp. 204-209, 1981.
K. Yamabe, et al. "Time-Dependent Dielectric Breakdown of Thin Thermally Frown SiO.sub.2 Films", IEEE Transactions on Electron Devices, vol. ED-32, No. 2, pp. 423-428, Feb. 1985.
Published by Engineering Department of Electronic Industries Association, "Procedure for the Wafer-Level Testing of Thin Dielectrics", JEDEC Standard No. 35, pp. 1-39, Jul. 1992.

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