Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-09-22
2002-12-10
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S401000, C713S502000, C327S158000
Reexamination Certificate
active
06493829
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device operating in synchronization with an external clock signal.
2. Description of the Background Art
In accordance with the increase in the speed of the memory system, the standard for the input/output timing of signals has become extremely stringent in semiconductor memory devices such as a SDRAM.
In a SDRAM, an internal clock signal in synchronization with an external clock signal is generated by a DLL circuit. That internal clock signal is employed as the trigger signal of the output of data and a strobe signal thereof. The DLL circuit includes a variable delay circuit delaying an external clock signal to generate an internal clock signal, an I/O replica circuit delaying the internal clock signal by a delay time obtained taking into consideration the input path of the external clock signal and the data output path to generate a dummy clock signal, and a phase comparator comparing the phases between the external clock signal and the dummy clock signal to control the delay time of the variable delay circuit according to the comparison result. Accordingly, the output timing of the data and the strobe signal thereof can be set in complete synchronization with the external clock signal.
Although the DLL circuits plays an important role in a SDRAM, the operation state of a DLL circuit could be monitored only indirectly by the output data and the strobe signal.
However, the DLL circuit could not be tested properly since the effect of the circuit block other than the DLL circuit cannot be removed.
SUMMARY OF THE INVENTION
In view of the foregoing, a main object of the present invention is to provide a semiconductor device that can have testing of the internal clock generation operation carried out easily and correctly.
According to an aspect of the present invention, a semiconductor device includes a variable delay circuit generating an internal clock signal in synchronization with an external clock signal, a phase comparator comparing phases of an external clock signal and an internal clock signal to output first and second control signals to increase/decrease the delay time of the variable delay circuit, an up/down counter counting the number of times the first and second control signals are output, an internal circuit carrying out a predetermined operation in synchronization with an internal clock signal, and an output circuit providing the signal of the internal circuit outside when in a normal operation and providing the count value of the up/down counter outside when in a test mode. Therefore, the operation of internal clock generation can be tested easily and correctly by monitoring the output signal of the output circuit during testing.
Preferably, the delay time of the variable delay circuit is controlled by the count value of the up/down counter. In this case, the structure is simplified.
Also preferably, the semiconductor device further includes a shift register controlling the delay time of the variable delay circuit by the output signal of a plurality of registers. In this case, the delay time of the variable delay circuit can be controlled easily.
Also preferably, each of the plurality of registers at the first stage side of the plurality of shift registers retains a signal of the first logic. Each of the other registers retains a signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the number of registers retaining the signal of the first logic.
Also preferably, one of the plurality of registers of the shift register retains a signal of the first logic. Each of the other registers retains a signal of the second logic. In this case, the delay time of the variable delay circuit is determined by the position of the register retaining the signal of the first logic.
Also preferably, the internal circuit is a memory circuit. The output circuit includes a switch circuit that passes data read out from the memory circuit in a normal operation mode and that passes the count value of the up/down counter when in a test mode, and a data output circuit providing outside the read out data and the count value passing through the switch circuit. In this case, the operation of the internal clock generation of the semiconductor memory device can be tested easily and correctly.
According to another aspect of the present invention, a semiconductor device includes a variable delay circuit generating an internal clock signal in synchronization with an external clock signal, a phase comparator comparing phases of an external clock signal and an internal clock signal to output first and second control signals to increase/decrease the delay time of the variable delay circuit, a shift register controlling the delay time of the variable delay circuit according to the output signal of a plurality of registers, an internal circuit carrying out a predetermined operation in synchronization with an internal clock signal, and an output circuit providing a signal of the internal circuit outside when in a normal operation mode, and providing the output signal of at least one register of each group outside when in a test mode. By monitoring the output signal of the output circuit in the test mode, the operation of the internal clock generation can be tested easily and correctly.
Preferably, the output circuit provides the output signals of the plurality of registers divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time can be reduced. Therefore, the signals of all the registers can be output even when the number of signals that can be output at one time from the output circuit is smaller than the number of registers.
Also preferably, the output circuit provides the output signal of a preselected register of each group in a test mode. In this case, the signal of one register out of each group is output. Therefore, the number of output signals per one time can be reduced.
Also preferably, the output circuit provides the output signals of a plurality of preselected registers out of a plurality of groups divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time can further be reduced.
Also preferably, the semiconductor device further includes a first logic circuit provided corresponding to each group to generate an OR, AND or exclusive-OR signal of the output signals of the plurality of registers belonging to a corresponding group. The output circuit provides the output signal of each first logic circuit in a test mode. In this case, the group corresponding to the head bit can easily be identified.
Also preferably, the output circuit provides the output signals of the plurality of logic circuits divided for output over a plurality of times in a time-divisional manner. In this case, the number of output signals per one time in the test mode can be reduced.
Also preferably, the plurality of registers of each group are further divided into a plurality of sub-groups. A determination circuit determines whether the logic of the output signal of the plurality of registers of each group matches or not, and selects the group does not match. The output circuit provides the output signal of at least one register of each sub-group belonging to the group selected by the determination circuit in a test mode. In this case, more detailed information can be obtained of the position of the head bit.
Also preferably, the test is divided into first and second tests. The output circuit provides the output signal of at least one register of each group in the first test mode, and provides the output signal of at least one register of each sub-group belonging to the group selected by the determination circuit in the second test mode. In this case, the number of output signals per one time can be reduced in the test mode.
Also preferably, the output circuit provides the output signal
Cao Chun
Lee Thomas
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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