Semiconductor device containing P-HDP interdielectric layer

Details Semiconductor device containing P-HDP interdielectric layer Semiconductor device containing P-HDP interdielectric layer

1998-11-25

2000-06-27

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438624, 438784, 438437, 438763, 438788, H01L 2176, H01L 214763

Patent

active

060806397

ABSTRACT:
Void formation is avoided without thermal treatment by a gap filling between electrically conductive elements such as stacked gates which are formed atop of isolation regions, with an oxide layer using a HDP technique. The oxide layer is doped with phosphorus to getter mobile ionic contaminants.

REFERENCES:
patent: 5621241 (1997-04-01), Jain
patent: 5679606 (1997-10-01), Wang et al.
patent: 5716890 (1998-02-01), Yao
patent: 5968610 (1999-10-01), Liu et al.

Affiliated with

Also associated with

Rating

Semiconductor device containing P-HDP interdielectric layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device containing P-HDP interdielectric layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device containing P-HDP interdielectric layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1784044