Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2003-05-30
2004-12-28
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S686000, C257S723000, C257S786000, C257S698000, C257S777000
Reexamination Certificate
active
06836025
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The present invention is based on Japanese priority applications No. 2002-158997 filed May 31, 2002, No. 2002-316076 filed Oct. 30, 2002 and No. 2003-127344 filed May 2, 2003, the entire contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a semiconductor device configured to be surface-mountable and manufacturing method thereof.
2. Description of the Related Art
In recent years, high-densification of semiconductor chips has progressed remarkably, and the size of semiconductor chips has been reduced. In connection with this, high-densification and high-functionalization of semiconductor devices have progressed, and a technique has been developed to integrally incorporate a plurality of semiconductor chips into one semiconductor device. For example, there is a semiconductor device in which a plurality of semiconductor chips of different kinds and functions are connected to each other and external connection electrodes are provided.
Although there is a multi-chip module (MCM) as one example which accommodates a plurality of semiconductor chips in one package, such a conventional MCM does not have a fine structure that is the same as a semiconductor chip having a recently developed fine structure.
Japanese Laid-Open Patent Application No. 2001-217381 discloses an example of a technique to accommodate a plurality of semiconductor chips in one package. With the technique disclosed in this patent document, a plurality of semiconductor chips are arranged on a mounting jig and copper posts are formed on electrodes of each semiconductor chip. Then, the semiconductor chips together with the copper posts are encapsulated by a seal resin using transfer molding, and a surface of the seal resin is grinded so as to expose the copper posts. After forming wiring (rearrangement wiring) on the surface of the seal resin on which the copper posts are exposed, external connection electrodes are formed on the rearrangement wiring.
Japanese Laid-Open Patent Application No. 2001-332643 discloses a technique similar to that disclosed in the above-mentioned patent document. This patent document discloses formation of a protective film on a back surface of each semiconductor chip.
Additionally, Japanese Laid-Open Patent Application No. 7-86502 discloses a technique wherein a plurality of semiconductor chips are accommodated in a recess formed in a substrate and rearrangement wiring is formed on the semiconductor chips and then external connection terminals are formed on the rearrangement wiring. With this technique, the depth of the recess is so that the circuit formation surface of each semiconductor chip aligns with the surface of the substrate.
Further, Japanese Laid-Open Patent Application No. 2002-110714 discloses a technique wherein a plurality of semiconductor chips are arranged with the circuit formation surfaces facing downward and a resin is filled between the semiconductor chips while setting the circuit formation surfaces of the semiconductor chips to be a flat surface by covering the back surfaces and side surfaces of the semiconductor chips. Thereafter, rearrangement wiring is formed on the side of the circuit formation surfaces so as to form external connection terminals.
Moreover, Japanese Laid-Open Patent Application No. 5-206368 discloses a technique wherein a plurality of semiconductor chips are mounted on a thermally conductive substrate, an insulating resin is filled between the chips and rearrangement wiring is formed by aluminum on the circuit formation surfaces.
Although the above-mentioned conventional technique is constituted by mounting a plurality of semiconductor chips in a side-by-side arrangement, many kinds of stack-type semiconductor devices, in which a plurality of semiconductor chips are stacked, have been developed.
As examples of document disclosing a stack-type semiconductor device, there are Japanese Laid-Open Patent Applications No. 2001-298149 and No. 2001-320015.
With the technology disclosed in Japanese Laid-Open Patent Application No. 2001-298149, an upper semiconductor chip is mounted inside a pad area (peripheral-arranged electrodes) of a lower semiconductor chip on which the upper semiconductor chip is stacked. Additionally, with the technique disclosed in Japanese Laid-Open Patent Application No. 2001-320015, conductive pillars (column-shaped metal members) are provided on a wiring layer on each of the stacked semiconductor chips.
With the technique disclosed in the above-mentioned Japanese Laid-Open Patent Applications No. 2001-217381 and No. 2001-332643, the semiconductor chips are encapsulated by a seal resin using transfer molding, and, thus, a pressure applied during the transfer molding may have an adverse affect on the semiconductor chips. Additionally, a large force may be exerted on the semiconductor chips also at the time of grounding of the seal resin surface after molding. Further, when the semiconductor chips are stacked, warp may occur due to contraction at the time of curing the seal resin on a mounting substrate (silicon wafer). Such a warp may have an adverse affect when the semiconductor chips are stacked.
Laid-Open Patent Application No. 7-86502, a high accuracy is required in the depth of the recess when forming the recess which accommodates semiconductor chips. Particularly, if the semiconductor chips become thin, a higher accuracy is required in the depth of the recess, which may be difficult to achieve.
Further, with the technique disclosed in Japanese Laid-Open Patent Application No. 2002-110714, a resin is provided on the back side of semiconductor chips, which causes a problem of poor heat radiation characteristic of the semiconductor chips. Moreover, warpage may occur in the semiconductor device due to the resin being cured on the back side of the semiconductor chips.
Moreover, according to the technique disclosed in Japanese Laid-Open Patent Applications No. 2002-110714 and No. 5-206368, a resin is filled between semiconductor chips after arranging the semiconductor chips at predetermined positions, and, thus, there may be a case in which a displacement of the semiconductor chips occurs when mounting the semiconductor chips or filling the resin. With this technique, it is impossible to remove the displaced chip.
Further, with respect to stacked type semiconductor device, in the technique disclosed in Japanese Laid-Open Patent Application No. 2001-298149, an upper semiconductor chip is mounted inside the pad area (peripheral arrangement electrode) of the lower semiconductor chip on which the upper semiconductor chip is stacked, semiconductor chips having the same size cannot be stacked. Moreover, with the technique disclosed in Japanese Laid-Open Patent Application No. 2001-320015, the manufacturing cost of a semiconductor device is increased due to the formation of the conductive pillars.
In the meantime, a semiconductor device which is formed by stacking semiconductor chips, generally the semiconductor chip is securely fixed to a substrate by covering the circumference of the semiconductor chip. Additionally, in a case where a plurality of semiconductor chips are mounted on a substrate such as a multi-chip module, a resin is filled between the semiconductor chips as disclosed in Japanese Laid-Open Patent Application No. 2002-110714. With such a filled resin layer, each semiconductor chip can be securely fixed to the substrate, and the semiconductor chips are insulated to each other.
The filled resin layer can be previously formed prior to mounting the semiconductor chips onto the substrate, or the resin may be filled after mounting the semiconductor chips onto the substrate.
When the above-mentioned filled resin layer is formed prior to mounting the semiconductor chip, a part of the filled resin layer formed on the substrate is removed so as to form an opening in which the surface of the substrate is exposed, and the semiconductor chip is mou
Aiba Yoshitaka
Fujisawa Tetsuya
Igawa Osamu
Ikumo Masamitsu
Matsuki Hirohisa
Flynn Nathan J.
Forde Remmon R.
Fujitsu Limited
Westerman Hattori Daniels & Adrian LLP
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