Semiconductor device comprising capacitor cells, bit lines,...

Details Semiconductor device comprising capacitor cells, bit lines,... Semiconductor device comprising capacitor cells, bit lines,...

1999-07-20

2003-06-10

Nguyen, Cuong Quang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000

Reexamination Certificate

active

06576946

ABSTRACT:

FIELD OF THE INVENTION
In general, the present invention relates to a dynamic random-access memory, such as a DRAM. More particularly, the present invention relates to a semiconductor device having a configuration comprising a DRAM and other semiconductor elements, such as a logic circuit.
BACKGROUND OF THE INVENTION
Miniaturization of a DRAM cell raises a problem in that it is difficult to assure that the capacitance of the capacitor for accumulating an electric charge will be large enough for cell operations due to the fact that the capacitance is reduced by the miniaturization. There have been proposed a variety of techniques to solve this problem. According to one of the techniques, a stack DRAM cell wherein an accumulation electrode is created typically over a word line.
In this memory cell, however, if a accumulator capacitor is created by utilizing the area of the plane portion, the capacitance of the capacitor is reduced as the memory cell is made smaller in size. For this reason, there have been proposed a variety of techniques for increasing the area of the physical shape of the capacitor in the thickness direction of the semiconductor substrate. Nevertheless, it is difficult to implement a DPAM having a capacity of at least 256 Mbit with any of the these techniques.
Concrete examples of the conventional technology are as follows. The capacitor structures shown in
FIGS. 1
to
3
/are referred to as an STC (Stacked Capacitor), a crown-STC and a FIN-STC, respectively. In each of the structures, one capacitor is provided for each cell. It should be noted that, in
FIGS. 1
to
3
reference numeral
0
denotes a semiconductor substrate and reference numeral
1
denotes an insulation film for separating elements from each other. Reference numerals
2
and
3
denote a word line and a bit-line contact plug, respectively. Reference numeral
4
denotes an accumulation-node contact plug and reference numeral
5
denotes a bit line. Reference numerals
7
and
9
denote a capacitor insulation film and a lower electrode, respectively. Reference numeral
14
denotes a capacitor insulation film and reference numeral
15
denotes an upper electrode.
Japanese Patent Laid-open No. Hei 4-83375 discloses a Capacitor structure for high density DRAM cells wherein three fences are created on an area occupied by an accumulation electrode by using first and second protrusions.
In addition, Japanese Patent Laid-open No. Hei 4-212449 discloses an example wherein two capacitors are provided, being stretched over two memory cells in order to secure a large capacitance in the conventional capacitor structure, while assuring a high integration density. For these capacitors, which have a configuration stretched over two memory cells, the capacitors are extended in the direction of the bit line.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to provide a semiconductor device which is capable of assuring a higher capacitance for a memory capacitor while securing a higher density of integration.
The present invention solves a variety problems that are inherent in the conventional technology. One problem involves the difficulty in securing a sufficient capacitance in a capacitor due to a limitation imposed by the fabrication technology to assure sufficient space between capacitors for a shrunk cell area accompanying high-scale integration and miniaturization. Another problem involves an unavoidably reduced yield, which inevitably results in a rising cost of manufacture caused by the fact that the structure of the capacitor is made complicated and the height of the capacitor is increased in order to obtain a sufficient capacitance of the capacitor.
In the case of the memory cell structure described above, as the miniaturization of the memory cell continues, the area occupied by the lower electrode of the capacitor can not help but be reduced. This is because a limitation on the miniaturization by the fabrication technology imposes a limit on the size of the area occupied by the lower electrode. To be more specific, in order to secure a space between capacitors, the cell area can not help reduced. Thus, in order to obtain a sufficient capacitance, the structure of the capacitor is made complicated and the height of the capacitor is increased. An increased number of manufacturing processes and finer processes inevitably lower the product yield and raise the cost of manufacture.
FIG. 4
is a diagram showing the structure of a capacitor disclosed in Japanese Patent Laid-open No. Hei 4-83375.
FIG. 4
is a top-view layout of two sets each serving as a unit. One of the sets comprises a first protruding lower electrode
21
and a second protruding lower electrode
22
. The other set comprises a first protruding lower electrode
23
and a second protruding lower electrode
24
. Three fences are used as the electrode surfaces of the capacitor. The three fences are a fence between the first protruding lower electrode
21
and the second protruding lower electrode
22
, a fence between the first protruding lower electrode
23
and the second protruding lower electrode
24
and a fence between the first protruding lower electrode
21
and the first protruding lower electrode
23
. In this capacitor structure, however, the first protruding lower electrode
21
and the second protruding lower electrode
22
are created by using a self-matching technique, while the first protruding lower electrodes
23
and
24
are created among themselves by using lithography technology. Thus, as miniaturization progresses, problems are created, such as a decreased yield of-similar products and an increased cost.
A first aspect of the present invention relates particularly to the structure of a stack capacitor cell (STC) and its manufacturing method. That is, a lower electrode of a capacitor for a memory is designed to comprise two portions, namely, a bottom and a wall-shaped body and the lower electrode is mounted in such a way that the longitudinal direction of the wall-shaped body is oriented toward the upper portion of the semiconductor substrate in order to increase the area of the capacitor electrode. In addition, the wall-shaped body and an insulation layer for the capacitor are created by using a so-called self-matching technique, while each layer is created by using the CVD (Chemical Vapor Deposition) method. It is to be noted that the use of a plurality of wall-shaped bodies is just natural and desirable from the capacity-enhancement point of view.
The self-matching technique provided by the present invention is a method whereby, once the position of a protruding body for creating a first wall-shaped body of a capacitor has been determined, members of the capacitor, that is, a second wall-shaped body and the insulation layer, are implemented without a mask process. If the CVD method is used in the creation of these layers, the film thickness of each of the layers can be adjusted with a high degree of freedom. Accordingly, it is possible to create a capacitor structure having a higher capacitance at a density that can be set freely without regard to the area of the memory cell.
According to a second aspect of the present invention, capacitors are created at contiguous locations over a plurality of memory cells which are laid out in the direction of the word line of a semiconductor memory device. Tn such a contiguous arrangement of capacitors, a capacitor can be created in a space between cells which is not used in the conventional design. As a result, the capacitance of the capacitor can be further increased.
An implementation by a combination of these two aspects of the present invention makes it possible to secure a capacitor having a high capacitance for a memory while assuring a high-density integration. For example, it is possible to implement a semiconductor memory device having a storage capacity of at least 256 Mbit.
In addition, by creating a lower electrode of a capacitor by using a plurality of wall-shaped bodies and by adopting the self-matching technique to produce a wall-shaped body

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