Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-10
2004-11-09
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C438S239000
Reexamination Certificate
active
06815747
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a capacitor.
2. Description of the Background Art
In a conventional semiconductor device such as a DRAM (dynamic random access memory), a capacitor is generally provided on an interlayer dielectric film formed on a semiconductor substrate.
A conventional semiconductor device having a capacitor is now described with reference to FIG.
43
.
In the conventional semiconductor device having a capacitor, two transistors
101
and
102
are formed inside element forming regions enclosed with element isolation films on a semiconductor substrate
100
. A vertically extending wire is connected to a source/drain region of the transistor
101
. Another vertically extending wire is connected also to a source/drain region of the transistor
102
.
A plurality of interlayer dielectric films
113
,
1100
and
1200
are formed above the transistors
101
and
102
in a stacked manner. A via plug
114
is embedded above the transistor
101
in the interlayer dielectric film
113
included in the plurality of interlayer dielectric films
113
,
1100
and
1200
.
Further, a capacitor lower electrode
115
is embedded in the interlayer dielectric film
113
. This capacitor lower electrode
115
is connected to the upper surface of the via plug
114
. A wiring layer
165
of the same layer as the capacitor lower electrode
115
located above the transistor
101
is embedded above the transistor
102
. The capacitor lower electrode
115
and the wiring layer
165
are flush with each other with reference to the main surface of the semiconductor substrate
100
. A wiring layer
1165
of the same layer as a capacitor upper electrode
1015
is embedded above the wiring layer
165
. The capacitor upper electrode
1015
and the wiring layer
1165
are flush with each other with reference to the main surface of the semiconductor substrate
100
.
In the semiconductor device shown in
FIG. 43
having the aforementioned structure, the interlayer dielectric film
1100
is formed above the transistors
101
and
102
, in order to form the capacitor above the transistor
101
. Further, the capacitor upper electrode
1015
is formed on an upper portion of the interlayer dielectric film
1100
located above the transistor
101
. The capacitor lower electrode
115
and the capacitor upper electrode
1015
form the capacitor connected to the source/drain region of the transistor
101
.
The interlayer dielectric film
1200
covering the interlayer dielectric film
1100
and the capacitor upper electrode
1015
is formed above the transistors
101
and
102
respectively. The interlayer dielectric film
1200
is an insulator film for filling up holes in a region other than that shown in
FIG. 43
, for example.
In the aforementioned semiconductor device shown in
FIG. 43
, the wiring layers
165
and
1165
are provided as dummy patterns corresponding to the capacitor lower electrode
115
and the capacitor upper electrode
1015
respectively. A large number of such wiring layers
165
and
1165
serving as dummy patterns are provided on the same level as the capacitor at substantially regular intervals in a direction parallel to the main surface of the semiconductor substrate
100
. In a CMP (Chemical Mechanical Polishing) step after formation of the capacitor, therefore, surface uniformity of the interlayer dielectric film
1200
is ensured after polishing.
In the aforementioned semiconductor device shown in
FIG. 43
, a large number of wiring layers
165
and
1165
serving as dummy patterns must be provided substantially at regular intervals in the direction parallel to the main surface of the semiconductor substrate
100
, in order to provide the capacitor. Therefore, the quantity of the material forming the dummy patterns is disadvantageously increased.
In the semiconductor device such as a DRAM, the capacitance of the capacitor is to be increased. In order to increase the capacitance of the capacitor, the opposite area of the capacitor upper electrode
1015
and the capacitor lower electrode
115
must be increased. Therefore, the sizes of the capacitor upper electrode
1015
and the capacitor lower electrode
115
may conceivably be increased in the direction parallel to the main surface of the semiconductor substrate
100
. When the size of the capacitor is increased in the direction parallel to the main surface of the semiconductor substrate
100
, however, it is difficult to refine the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of attaining both of an effect of increasing the electrostatic capacitance of a capacitor and an effect of reducing the quantity of a material forming a dummy pattern corresponding to the capacitor without increasing the size of the capacitor in a direction parallel to the main surface of a semiconductor substrate.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate, an interlayer dielectric film having an upper surface parallel to the main surface of the semiconductor substrate and including a first recess portion formed at a prescribed depth from the upper surface and a second recess portion formed at a prescribed depth from the upper surface, and a first conductive film, filling up the first recess portion, having an upper surface continuous with the upper surface.
The semiconductor device according to the first aspect of the present invention further comprises a capacitor lower electrode provided along the surface of the second recess portion, a capacitor dielectric film provided along the surface of a recess portion defined by the capacitor lower electrode and a capacitor upper electrode provided in a recess portion defined by the capacitor dielectric film.
According to the aforementioned structure of the inventive semiconductor device, both of an effect capable of increasing the electrostatic capacitance of a capacitor and an effect capable of reducing the quantity of a material forming a dummy pattern corresponding to the capacitor can be attained without increasing the size of the capacitor in the direction parallel to the main surface of the semiconductor substrate.
A semiconductor device according to a second aspect of the present invention comprises an element forming region, formed on a semiconductor substrate, provided with a transistor, an element isolation film, enclosing the element forming region, having a recess portion formed at a prescribed depth from the upper surface and a capacitor provided in the recess portion and electrically connected to a source/drain region of the transistor.
According to the aforementioned structure of the inventive semiconductor device, both of an effect capable of increasing the electrostatic capacitance of the capacitor and an effect capable of reducing the quantity of a material forming a dummy pattern corresponding to the capacitor can be attained without increasing the size of the capacitor in a direction parallel to the main surface of the semiconductor substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
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Kosugi Takeshi
Oashi Toshiyuki
McDermott Will & Emery LLP
Pham Long
Renesas Technology Corp.
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