Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-01
2003-08-19
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S488000, C257S489000, C257S492000, C257S493000, C257S640000, C257S646000, C257S649000
Reexamination Certificate
active
06608351
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device having a semiconductor body comprising a high-voltage circuit element having a surface region adjacent to a surface of the semiconductor body, which surface region is covered with an electrically insulating layer and in which two zones are formed at some distance from each other, between which a high voltage can be applied, during operation, and a part of the insulating layer, situated above a part of the substantially single-conductivity type surface region situated between the two zones, is provided with a semi-insulating layer provided with two connections by means of which a high voltage can also be applied across the semi-insulating layer. Such a device is known from, inter alia, the patent document U.S. Pat. No. 5,107,323.
The high-voltage circuit element may be, for example, a diode or a junction field-effect transistor (JFET) or a lateral field-effect transistor of the DMOST type.
If no additional measures are taken, such high-voltage devices often are adversely affected by charge-creep effects via the synthetic resin envelope during high-voltage operation, particularly at a comparatively high temperature. At said high voltage, electric-charge transport takes place, for example transport of ions in the envelope, causing the voltage distribution to be changed. This will influence the properties and the quality of the device if a protective screen is not provided. For example, the breakdown voltage may be reduced and/or the on-resistance increased, i.e. the device is not stable.
The influence of charge creep in the synthetic resin can be limited by providing a resistive layer or a semi-insulating layer on the device, as described in the patent document U.S. Pat. No. 5,107,323, as a result of which a certain voltage distribution is impressed upon the device. In practice it has been found, however, that also in this case instability often occurs, as a result of which the on-resistance is increased and/or the breakdown voltage reduced with the lapse of time.
SUMMARY OF THE INVENTION
It is an object of the invention to provide, inter alia, a high-voltage semiconductor device which remains stable after having been in operation for a prolonged period of time. The invention further aims at providing such a device, which can be manufactured using customary processes and without introducing additional process steps.
To achieve this, a semiconductor device of the type described in the opening paragraph is characterized in accordance with the invention in that electroconductive regions are provided between the two connections of the semi-insulating layer, the distribution of said electroconductive regions being such that a non-linear potential distribution is obtained in the semi-insulating layer.
The invention is based, inter alia, on the recognition that if a voltage is applied across the resistive layer for a certain period of time, the semi-insulating layer will eventually impress a linear potential gradient upon the device. The rate at which this takes place depends upon the resistivity. However, such a linear potential gradient does not have to correspond to the potential gradient at the surface of the semiconductor body, which is often not linear. When the high voltage across the resistive layer disappears, the electric charge in the resistive layer will not disappear immediately, so that it will continue to exert influence for some time. This may lead to an increase of the on-resistance of the circuit element. By providing the resistive layer with a non-linear distribution of conductive regions, it becomes possible to obtain a non-linear potential gradient in the resistive layer, which non-linear potential gradient is adapted to the potential gradient at the surface of the semiconductor body, so that the above-mentioned instability is avoided.
An embodiment of a device in accordance with the invention is characterized in that the zones are provided with contacts which have been formed jointly with the conductive regions from a common conductive metal layer. As the conductive regions and the metal contacts of the zones can be simultaneously formed, additional process steps to provide the conductive regions are avoided.
A favorable embodiment of a device in accordance with the invention, wherein the semi-insulating layer is formed during the provision of a passivating layer, is characterized in that the semi-insulating layer is formed by a passivating layer enriched by silicon which is applied to the electrically insulating layer and the conductive regions. The resistance of the semi-insulating layer can be advantageously adjusted by means of the quantity of silicon by which the passivating layer is enriched. For the passivating layer use can be made, for example, of silicon nitride, which is a customary material in the semiconductor technology.
The invention can be advantageously used in the manufacture of various high-voltage structures. A semiconductor device in accordance with the invention, wherein particular advantages are achieved is characterized in that said zones form a source zone and, separated therefrom by an intermediate channel region, a drain zone of a field effect transistor, the connections of the semi-insulating layer being connected to the source zone and the drain zone. The transistor may be, for example, a JFET, a lateral MOS transistor, a lateral DMOS transistor or a lateral IGBT (lateral Isolated Gated Bipolar Transistor).
An important preferred embodiment of a semiconductor device in accordance with the invention is characterized in that the circuit element is of the RESURF type. As is well known, in a RESURF device, a high breakdown voltage is obtained by a reduction of the electric fields at the surface of the semiconductor body. To achieve this, the device is embodied such that the layer wherein these fields develop is depleted across its entire thickness before breakdown has occurred. Theoretical examinations have shown that, for this purpose, the layer must satisfy the condition that the product of the doping concentration N and the thickness of the layer is approximately equal to 10
12
atoms per cm
2
. By applying the RESURF principle in a device in accordance with the invention, inter alia, the advantage is obtained that in the event of a very rapid voltage increase, breakdown is avoided even if the semi-insulating layer has not yet been able to exert influence.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 4947232 (1990-08-01), Ashida et al.
patent: 5107323 (1992-04-01), Knolle et al.
patent: 0182422 (1986-05-01), None
patent: 0615291 (1994-09-01), None
Huizing Hendrik Gezienus Albert
Ludikhuize Adrianus Willem
Meeuwsen Constantinus Paulus
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