Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-26
2001-01-23
Abraham, Fetsum (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S751000, C257S752000, C257S763000, C257S764000, C257S765000, C257S758000, C257S760000, C257S348000, C257S349000, C257S351000, C257S353000, C257S355000
Reexamination Certificate
active
06177707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device comprising a glass supporting body onto which an insulating substrate is attached by means of a layer of an adhesive, said insulating substrate being provided, on its first side facing the supporting body, with a surface on which a semiconductor element is formed in a layer of a semiconductor material and on which a metalization with a pattern of conductor tracks is provided.
The semiconductor element may be a single diode or transistor, but it may alternatively be an integrated circuit comprising a large number of transistors. The metalization may include conductor tracks which interconnect semiconductor elements, but it may alternatively include conductor tracks which are provided with connection electrodes (bonding pads) enabling external contact of the semiconductor device. The metalization may also comprise passive elements, such as capacitors, resistors and coils.
2. Description of the Related Art
The described semiconductor device is particularly suited for processing signals of very high frequencies. If integrated circuits are formed, as customary, on an approximately 500 &mgr;m thick slice of a semiconductor material, only an approximately 1 to 3 &mgr;m thick top layer of this slice is used for forming said integrated circuits. The semiconductor material situated below this thin top layer, i.e. the semiconductor substrate, adversely affects the high-frequency behavior of these circuits, inter alia by the formation of parasitic capacitances between semiconductor elements and this semiconductor substrate. In addition, it is impossible to form high-quality coils on a semiconductor substrate of such thickness, because, during operation, substantial eddy currents are generated in the thick semiconductor substrate situated under the coils. Since, in the semiconductor device mentioned in the opening paragraph, the layer of semiconductor material, having a thickness, for example of 1 to 3 &mgr;m, is very thin, said undesirable influences are substantially counteracted.
In practice, the semiconductor device can be mounted with the glass supporting body in a customary envelope or even on a customary printed circuit board. In an envelope as well as on such a printed circuit board, there is a metalization with conductor tracks for contacting the semiconductor device. The printed circuit board is also provided with a metalization having conductor tracks to connect the semiconductor device to other semiconductor devices and to passive elements, such as resistors and capacitors. The glass supporting body is sandwiched between the metalization of the semiconductor device and said other metalization, so that parasitic capacitances between these metalizations are small.
As indicated hereinabove, the parasitic capacitances in the semiconductor device are very small. As a result, the parasitic currents flowing during processing of high-frequency signals are very small. By virtue thereof, the power consumption of the semiconductor device is small, which is particularly advantageous for application in mobile telephony, where signals with a frequency of approximately 2 GHz must be processed and the power must be supplied by batteries. The power consumption may be a factor of 50 smaller than that of a customary integrated circuit, which is formed on an ordinary, relatively thick slice of semiconductor material.
U.S. Pat. No. 5,646,432 discloses a semiconductor device of the type mentioned in the opening paragraph, in which the semiconductor element and the metalization are covered with an approximately 2 &mgr;m thick passivating layer of silicon nitride, and a less than 2 &mgr;m thick planarizing layer is provided between this passivating layer and the layer of adhesive. The layer of adhesive has a thickness of 10 to 20 &mgr;m.
Although parasitic capacitances, which are formed between the metalization of the semiconductor device and the metalization on a printed circuit board on which the semiconductor device is mounted, are small already, it is desirable to minimize these as much as possible in connection with the power consumption. If the glass supporting body has a dielectric constant &egr;
r
of approximately 6.5 and a thickness of 400 &mgr;m, then the capacitance between a conductor track having a width of 1 &mgr;m and the metalization on the printed circuit board is approximately 26.10
−18
F per &mgr;m of length of the conductor track. This capacitance can be reduced by employing a supporting body having an &egr;
r
which is lower than that of glass. However, this is not a practical solution because such materials, for example quartz, are very expensive. Also the use of a thicker supporting body is impractical because, for example, doubling the thickness to 800 &mgr;m only results in a reduction of said capacitance by approximately 10%. Not only is the increase in thickness of little avail, it also results in a semiconductor device whose thickness is too large and impractical. A practical thickness for the glass supporting body is approximately 400 &mgr;m. In this case, the overall thickness, i.e. including the layer of adhesive and the insulating substrate, is comparable to that of customary semiconductor slices, so that, for example, to envelope the semiconductor device use can be made of equipment which is customarily employed for enveloping semiconductor slices.
SUMMARY OF THE INVENTION
It is an object of the invention to further reduce the power consumption of the above-described device, without the necessity of employing a glass supporting body of impractical thickness or a supporting body of an impractical material. To achieve this, the device mentioned in the opening paragraph is characterized, in accordance with the invention, in that an insulating layer having a dielectric constant &egr;
r
below 3 is provided between the metalization formed on the substrate and the layer of adhesive. The invention is based on the realization that the size of said parasitic capacitances is predominantly determined by the dielectric constant of the dielectric which is closest to the conductors, and that the use of an only relatively thin layer of a material having a relatively low &egr;
r
between the metalization of the semiconductor device and the glass supporting body results in a relatively large reduction of said parasitic capacitances. The measure in accordance with the invention enables the capacitances between the metalization of the semiconductor device and the metalization on a printed circuit board on which the semiconductor device is mounted to be reduced substantially. By using a layer having an &egr;
r
of 2.5 and a thickness of approximately 25 &mgr;m, for example, the capacitance, as in the above-mentioned example, between an 1 &mgr;m wide conductor track and the metalization on the printed circuit board is reduced by 40% when use is made of a 400 &mgr;m thick glass supporting body with an &egr;
r
of 6.5. The power consumption is reduced by practically the same amount.
Preferably, the insulating layer having a dielectric constant &egr;
r
below 3 is also provided between the conductor tracks of the metalization. In the known, described semiconductor device, an approximately 2 &mgr;m thick passivating layer of silicon nitride is provided between the metalization and the layer of an adhesive. Such a layer has a relatively large &egr;
r
of approximately 7.5. As a result, the parasitic capacitances between the conductor tracks of the metalization are relatively large. These parasitic capacitances are substantially reduced by also providing the insulating layer between the conductor tracks.
Preferably, the insulating layer is a layer of parylene or benzocyclobutene. Such a dielectric has a dielectric constant &egr;
r
of approximately 2.5 . A semiconductor device which can be readily manufactured is characterized in that both the insulating layer having a dielectric constant &egr;
r
below 3 and the layer of an adhesive are layers of benzocyclobutene. Preferably, the layer
Dekker Ronald
Maas Henricus G. R.
Van Deurzen Maria H. W. A.
Abraham Fetsum
Biren Steven R.
U.S. Philips Corporation
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