Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-17
2001-09-04
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S332000
Reexamination Certificate
active
06285057
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to a semiconductor device that combines a vertical-channel trench-substrate field effect device with a Metal-Oxide-Silicon Field Effect Transistor (MOSFET) structure and to a method for its manufacture.
2. Description of the Related Art
The performance of MOSFET devices (for example, their speed and power consumption) can be affected by the level of substrate current exiting the MOSFET device. For example, the snapback voltage and/or holding voltage of a conventional N-channel MOSFET ESD device, under high drain and gate bias conditions, can be degraded by substrate current (made up of carriers, i.e. holes, generated through impact ionization) exiting the channel region of the N-channel MOSFET device and flowing to a semiconductor substrate underlying the N-channel MOSFET device.
The use of Silicon-On-Insulator (SOI) technology provides for a MOSFET device to be electrically isolated from an underlying semiconductor substrate by an insulating layer. See S. Wolf,
Silicon Processing for the VLSI Era, Volume
2
—Process Integration,
66-75, Lattice Press (1990). Although SOI technology can suppress the level of substrate current exiting a MOSFET device, it does not provide a means for independently and controllably tuning the level of substrate current, and hence the performance, of a MOSFET device.
Still needed in the field, therefore, is a semiconductor device that provides a means for independently and controllably tuning the substrate current, and hence the performance, of a MOSFET device. Also needed is a process for manufacturing such a semiconductor device that is compatible with conventional integrated circuit (IC) processing techniques.
SUMMARY OF THE INVENTION
The present invention provides a semiconductor device wherein the substrate current, and hence the performance, of a MOSFET structure can be independently and controllably tuned (i.e. regulated). In this regard, the term “independently” refers to the ability to regulate the substrate current exiting the MOSFET structure using an input signal (for example, an applied potential bias) to the semiconductor device that is not an input signal to the MOSFET structure itself. In other words, the input signals that control the level of the substrate current exiting the MOSFET structure are exclusive of those to the MOSFET structure. Semiconductor devices according to the present invention include a semiconductor substrate of a first conductivity type, a MOSFET structure disposed on the semiconductor substrate, and at least one vertical-channel trench-substrate field effect device disposed in the semiconductor substrate. The vertical-channel trench-substrate field effect device includes a vertical-channel region beneath the MOSFET structure.
During operation of semiconductor devices according to the present invention, substrate current exiting the MOSFET structure can be independently and controllably tuned by “pinching-off” the vertical-channel region of the vertical-channel trench-substrate field effect device. The vertical-channel region can be “pinched-off” (i.e. narrowed, either partially or completely) by applying a potential bias to the vertical-channel trench-substrate field effect device.
In one embodiment of a semiconductor device according to the present invention, the MOSFET structure includes a gate silicon dioxide layer on the semiconductor substrate, a silicon gate (e.g., a polysilicon gate or an amorphous silicon gate) overlying the gate silicon dioxide layer, and source and drain regions of a second conductivity type in the semiconductor substrate. The vertical-channel trench-substrate field effect device of this embodiment includes an expanded trench that extends from the upper surface of the semiconductor substrate to beneath the MOSFET structure, as well as a dielectric shallow trench spacer (e.g., a silicon dioxide or silicon nitride dielectric shallow trench spacer) disposed along an upper portion of the sidewall of the expanded trench. Furthermore, the dielectric shallow trench spacer is adjacent to the source and drain regions of the MOSFET structure. The vertical-channel trench-substrate field effect device further includes a silicon dioxide (SiO
2
) trench liner layer disposed on those portions of the sidewalls of the expanded trench that are not covered by the dielectric shallow trench spacer, as well as an electrically conductive trench fill layer (e.g., in-situ doped polysilicon) in the expanded trench. The vertical-channel region can be “pinched-off,” and the substrate current independently and controllably tuned, by applying a potential bias to the electrically conductive trench fill layer. This potential bias can be applied to the electrically conductive trench fill layer by means of an electrical contact to the electrically conductive trench fill layer.
Also provided is a process for manufacturing a semiconductor device according to the present invention that is compatible with conventional integrated circuit (IC) manufacturing techniques. The process includes the step of first providing a semiconductor substrate (for example, a silicon substrate), followed by the formation of a shallow trench in the semiconductor substrate. The shallow trench demarcates an active area region in the semiconductor substrate. Dielectric shallow trench sidewall spacers are then formed on the sidewalls of the shallow trench, followed by an enlargement, by isotropic silicon etching, of the shallow trench to form an expanded trench that extends beneath the active area region and defines a vertical-channel region thereunder. A SiO
2
trench liner layer is subsequently formed on the surfaces of the expanded trench and an electrically conductive trench fill layer (for example, an in-situ doped polysilicon layer) is then formed in the expanded trench. Finally, a MOSFET structure is fabricated on the semiconductor substrate in the active area region.
REFERENCES:
patent: 5770878 (1998-06-01), Beasom
patent: 5895951 (1999-04-01), So et al.
patent: 6043543 (2000-03-01), Klose
S. Wolf,Silicon Processing for the VLSI Era, vol. 1—Process Technology, pp. 185, 522 (Lattice Press, 1986).
S. Wolf,Silicon Processing for the VLSI Era, vol. 2—Process Integration, pp. 66-75, 350 (Lattice Press, 1990).
R.S. Muller and T.I. Kamins,Device Electronics for Integrated Circuits—Second Edition, pp. 436-437 (John Wiley & Sons, 1986).
Hopper Peter J.
Pichler Christoph
Meier Stephen D.
National Semiconductor Corporation
Stallman & Pollack LLP
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