Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
1999-07-08
2002-01-01
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S622000, C257S623000
Reexamination Certificate
active
06335559
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of etching a semiconductor wafer, particularly of a compound semiconductor, in order to facilitate cleaving of devices from the wafer, and to devices cleaved by such a method.
BACKGROUND ART
Semiconductor wafers are conventionally cleaved by inscribing or scoring with a diamond tipped stylus, marks or lines into the surface of the wafer. The inscribing is done after the processing of the devices, usually by placing the device on an adhesive mat. After inscribing a number of lines in one direction, the wafer is struck to separate the wafer into bars. With the bars still held in place, the wafer is then rotated through 90° and inscribed again, before being struck again to separate each device from each bar. The semiconductor device is then subjected to further processing, for example for incorporation into a chip or other package.
The scribing process suffers from a number of limitations. First, scoring of the surface is inherently a destructive process, and causes minute cracks and other imperfections along the length and radiating from the ends of the line. Such imperfections cause irregularities in the cleave planes, and variability of dimensions between devices. Furthermore, debris from the inscribing process can interfere mechanically, electrically or optically with the finished device, and must be washed off the cleaved bars or devices prior to any soldering to a mount or heat sink and bonding to wires. Washing carries the risk of inadvertent contamination of the external surfaces of the devices. These effects are a particular problem with compound semiconductor devices, such as edge emitting laser diodes, light emitting diodes and detectors.
The irregular damage caused during inscribing can be reduced if stylus speed is kept low. In practice, however low stylus speed is a significant inconvenience. For example, a compound semiconductor wafer 32 mm square takes between three and four hours to inscribe, cleave and wash, using an inscribing machine that costs about $70,000.
The inscribing process typically cuts about 2 &mgr;m into the top surface of a device. In many optical devices, the active optical layer, for example the stripe in a gain guided semiconductor laser, is at a depth less than this. Since imperfections in a cleave plane across an optical facet must be avoided, it is not possible to scribe across the width of the wafer in one direction. Therefore, it is conventional for short nicks to be inscribed along opposite edges of the wafer at intervals equal to the length of a semiconductor optical device. Splitting the wafer into bars is then initiated from aligned pairs of these nicks. If all is well the cleave propagates across the wafer to the opposite edge. This avoids imperfections in the facet, but unfortunately, micro-cracks from the ends of the nicks cause variability in the width of the bars and hence length of the devices. (In the transverse direction, the inscription can be across the full width of the bars, causing lower dimensional variation.)
For example, in devices formed from bars 350 &mgr;m long, an acceptable variability in the length of the device may be ±10 &mgr;m. If a pair of adjacent cracks defining the length of a bar both deviate significantly in opposite directions, the width of the bar is outside this specification, resulting in rejection of every device cleaved from the bar, and most likely the adjacent bar. Since each bar contains about 150 devices, such a fault likely results in the rejection of 300 devices.
The fact that the nicks do not extend across the wafer also carries the risk that a crack will not propagate fully across the wafer or that the wafer will break up irregularly when struck. These factors, and contamination due to debris or the wash, can have a serious effect on the yield of the process used to form the semiconductor devices.
Patent document JP 2039481 A proposes the use of V-shaped grooves etched in a region 1 to 3 mm from the edge of a wafer, as an aid to cleave initiation. The V-grooves need to be etched either directly into the bare substrate prior to formation of all the overlying layers, or prior to the final formation of laser stripes and contacts. The V-grooves cannot extend across the full width of the wafer because these would interfere with the laser stripe, and it is still necessary to cleave the wafer in one direction by the conventional scribing and striking method.
It is an object of the invention to provide a semiconductor manufacturing process and a device from such a process, that addresses some of these problems.
SUMMARY OF THE INVENTION
One aspect of the invention provides a semiconductor device cleaved from a wafer comprising a substrate and grown upon the substrate one or more layers, the cleaves thereby defining two pairs of parallel edges of the device, characterised in that each of the cleaves has been guided by a groove etched through the grown layers and partly into the substrate.
Also according to another aspect of the invention, there is provided a semiconductor wafer comprising a substrate and grown upon the substrate one or more layers, and grooves etched through the grown layers and partly into the substrate, characterised in that the grooves are arranged in a grid-like pattern to define cleave planes and hence edges of an array of semiconductor devices.
The semiconductor device may be a compound semiconductor device. The layers grown on the substrate will in general comprise semiconductor, insulating or conducting layers defining the electrical and/or optical properties of the device.
The pairs of edges will in general be orthogonal pairs defining the edges of a square or rectangular semiconductor device.
The groove may have a wall that extends at least partly along an edge of the device, or the groove may extend fully along an edge of the device.
In a preferred embodiment, a first pair of parallel edges is at right angles to a second pair of parallel edges, in which each one of the first pair of edges has a groove wall extending fully therealong, and each one of the second pair of edges has a groove wall extending only partly therealong.
Then, if the device has an active optical region within the grown layers, with the optical region extending to an edge of the device, that portion of the edge may have no such groove wall, so that the portion of the edge of the device having the active optical region is defined by a cleave plane.
Because etch rates for a groove can depend upon the crystal orientation of the material, it is advantageous if two adjacent edges each have a groove wall that extends at least partly along an edge of the device, with at least one of the groove walls not extending to a corner defined by the junction of the adjacent edges. In this way, preferential etching at a corner between adjacent groove walls can be avoided.
The invention also provides a manufacturing process for a semiconductor wafer, comprising the steps of:
i) forming a semiconductor substrate;
ii) growing upon the substrate one or more layers;
iii) etching grooves through the grown layers and partly into the substrate, characterised in that the grooves are arranged in a grid-like pattern to define cleave planes and hence edges of an array of semiconductor devices.
Once the wafer has been formed, the semiconductor device may be formed by cleaving the wafer along the grid-like pattern of grooves to separate the devices.
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Cruz Lourdes
Hewlett--Packard Company
Lee Eddie
LandOfFree
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