Electronic digital logic circuitry – Reliability – Parasitic prevention in integrated circuit structure
Reexamination Certificate
2002-04-23
2004-06-01
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Reliability
Parasitic prevention in integrated circuit structure
C326S026000, C326S101000, C327S382000, C327S403000
Reexamination Certificate
active
06744273
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and particularly relates to a semiconductor device reducing noise to a signal line which can transmit a signal at high speed from an adjacent wiring.
2. Description of the Background Art
There has been known hitherto, as one of methods for reducing noise to a signal line transmitting a signal at high speed, Japnaese Patent Laying-Open No. 2000-307065 discloses a method for allowing two adjacent wirings arranged in parallel on the both sides of a signal line, respectively, to transmit a signal equal in phase and amplitude to a signal transmitted by the signal line.
That is, referring to
FIG. 11
, if noise to a signal line
21
from adjacent wirings
22
and
23
is to be reduced, adjacent wirings
22
and
23
are allowed to transmit a signal equal in phase and amplitude to a signal transmitted by signal line
21
.
Driving means
12
to
14
drive adjacent wiring
22
, signal line
21
and adjacent signal line
23
to transmit the signals, respectively.
A conventional semiconductor device includes a switch circuit
11
and switch circuit
11
selectively supplies a signal equal in phase and amplitude to the signal transmitted by signal line
21
to adjacent wirings
22
and
23
so that the selected adjacent wiring transmits the signal.
Switch circuit
11
consists of terminals
15
and
16
and a switch S
1
. Terminal
15
is connected to signal line
21
and terminal
16
is connected to a ground terminal
17
. Switch S
1
is connected to terminal
15
or
16
by a select signal SEL to apply the signal on signal line
21
or a signal having a ground voltage to driving means
12
and
14
.
If a signal is transmitted by signal line
21
at high speed, switch circuit
11
is connected to terminal
15
by select signal SEL to apply a signal equal in phase and amplitude to the signal to be transmitted by signal line
21
to driving means
12
and
14
. Then, driving means
12
and
14
drive adjacent wirings
22
and
23
to transmit the signal equal in phase and amplitude to the signal to be transmitted by signal line
21
. As a result, noise from adjacent wirings
22
and
23
to signal line
21
is effectively eliminated.
However, since the conventional method for reducing noise from the adjacent wirings to the signal line is intended to reduce noise to the signal line between the signal line and the adjacent wirings arranged in the same plane, if another adjacent wiring exists in a perpendicular direction to the signal line, the noise to the signal line from the adjacent wiring existing in the perpendicular direction thereto cannot be disadvantageously reduced.
In other words, although the noise from the adjacent wiring to the signal line between the signal line and the adjacent wiring formed in the same plane can be reduced by allowing the signal line and the adjacent wiring to transmit signals equal in phase and amplitude, noise from another adjacent wiring existing in the perpendicular direction to the signal line cannot be reduced. In this case, as shown in
FIG. 12
, if an adjacent wiring existing in the perpendicular direction to the signal line is allowed to transmit a signal SGLS after a logical level on the signal line is fixed to H (logical high) level, then the signal on the signal line is turned into a signal SGLM on which noise is superimposed. If the noise is much, the logical level on the signal line disadvantageously turns into L (logical low) level.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device capable of reducing noise to a signal line from a part of adjacent wirings if a plurality of adjacent wirings adjacent the signal line exist, and capable of further reducing noise from another adjacent wiring to the signal line.
It is another object of the present invention to provide a semiconductor device capable of reducing noise between a signal line and an adjacent wiring formed in the same plane, and capable of further reducing noise to the signal line from an adjacent wiring existing in a perpendicular direction to the signal line.
According to this invention, a semiconductor device includes: a signal line transmitting a signal at high speed; first and second adjacent wirings provided at positions for forming line capacitances together with the signal lines, respectively, in parallel to the signal line; and a capacitance control circuit forming between the signal line and the second adjacent wiring a second line capacitance higher than a first capacitance formed between the signal line and the first adjacent wiring.
In the semiconductor device according to this invention, the second line capacitance which is higher than the first line capacitance formed between the signal line and the first adjacent wiring, is formed between the signal line and the second adjacent wiring out of the first and second adjacent wirings adjacent the signal line. Also, the first adjacent wiring is allowed to transmit a signal. According to this invention, therefore, it is possible to reduce noise from the first adjacent wiring to the signal line.
Preferably, the capacitance control circuit supplies charges for forming the second line capacitance to the second adjacent wiring when a potential on the signal line is constant.
The charges are supplied to the second adjacent wiring and the second line capacitance higher than the first line capacitance is formed between the signal line and the second adjacent wiring. According to this invention, therefore, by controlling the quantity of charges supplied to the adjacent wirings, it is possible to control the magnitude of the second line capacitance. As a result, even if the magnitude of the first line capacitance is changed by the signal transmitted by the first adjacent wiring, it is possible to reduce noise from the first adjacent wiring to the signal line by controlling the quantity of charges supplied to the second adjacent wiring.
Preferably, the capacitance control circuit decreases charges on the second adjacent wiring in a certain ratio and thereby forms the second line capacitance when the potential on the signal line is held to be high.
While the charges are supplied to the signal line, the charges are supplied to the second adjacent wiring so as to decrease the charges in a certain ratio. In addition, the second line capacitance determined by the charges supplied to the signal line is formed between the signal line and the second adjacent wiring. According to this invention, therefore, it is possible to easily form the second line capacitance.
Preferably, the capacitance control circuit includes: a first path for directly applying charges constituting a same signal as the signal applied to the signal line, to the second adjacent wiring; a second path for applying the charges to the second adjacent wiring through a resistance; and a switch selectively connecting one of the first and second paths to the second adjacent wiring, and the switch connects the first path to the second adjacent wiring when a signal to be transmitted at high speed is applied to the signal line, and connects the second path to the second adjacent wiring when a potential on the signal line is constant.
The capacitance control circuit supplies a signal equal in phase and amplitude to the signal supplied to the signal line, to the second adjacent wiring when the signal line is allowed to transmit the signal at high speed. In addition, when charges on the signal line are held to be constant, the capacitance control circuit applies charges to the second adjacent wiring so that the charges are decreased in a certain ratio. According to this invention, therefore, it is possible to reduce noise from the adjacent wirings to the signal line in response to each mode.
Preferably, the semiconductor device further includes a test mode entry circuit generating a test mode entry signal, and the capacitance control circuit applies charges constituting an inverted signal inverted from a signal applied
Kitagawa Makoto
Kono Takashi
Chang Daniel D.
Renesas Technology Corp.
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