Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2000-11-06
2003-12-02
Fahmy, Jr., Wael (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S332000, C438S337000, C438S339000, C438S589000
Reexamination Certificate
active
06656810
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a MOS (Metal Oxide Semiconductor) transistor having a recess structure formed on a SOI (Semiconductor on Insulator) substrate and method for fabricating the same.
A transistor formed by using a SOI substrate is attracting attention as a device having the superior electrical characteristics of a low threshold voltage, a good sub-threshold characteristic, absence of parasitic bipolar effect and so on as compared with the conventional transistor formed by using a bulk semiconductor substrate, and accordingly, researches on the transistor are being energetically conducted.
The SOI substrate has a structure in which an insulating layer is formed on a silicon substrate and a silicon layer (referred to as a SOI layer hereinafter) is formed on the insulating layer. A MOS transistor formed on such a SOI substrate generally has a structure as shown in FIG.
11
. in regard to the SOI wafer where an insulating layer
102
and a SOI layer
103
are formed on a silicon substrate
101
, a gate electrode
114
is formed on the SOI layer
103
via a gate oxide film
112
, and thereafter, low-concentration impurity ions are implanted using the gate electrode
114
as a mask to form LDD (lightly doped drain) regions
115
and
115
on both sides of a channel region
119
. Further, oxide film spacers
116
and
116
are formed on the side wall sides of the gate electrode
114
, and thereafter, high-concentration ion implantation is executed using the gate electrode
114
and the oxide film spacers
116
and
116
as a mask to form a source junction region
117
and a drain junction region
118
. In the thus-formed MOS transistor, the channel region
119
is formed with a small thickness of 50 to 150 nm in order to improve the carrier mobility, and therefore, the source junction region
117
and the drain junction region
118
are similarly reduced in thickness. As a result, the resistances of the source junction region
117
and the drain junction region
118
themselves increase, and this leads to the problem that the operating speed of the MOS transistor is reduced to degrade the device characteristics.
In order to solve the above problems, the following semiconductor device fabricating methods (1) and (2) have conventionally been proposed.
(1) The Semiconductor Device Fabricating Method Disclosed in the Prior Art Reference of Japanese Patent Laid-Open Publication No. HEI 9-8308
FIGS. 12A through 12E
are process charts for explaining the semiconductor device fabricating method disclosed in the prior art reference of Japanese Patent Laid-Open Publication No. HEI 9-8308. In the SOI substrate constructed of a silicon substrate
201
, an insulating layer
202
and a SOI layer
203
, the thickness of the SOI layer
203
is made to have a thickness of 300 to 500 nm. The SOI layer of a portion where a channel region and an LDD region are formed is etched using a photosensitive film
222
as a mask to reduce the film thickness of the portion of the SOI layer
203
to a specified thickness, forming a trench
223
(FIG.
12
A). Subsequently, a gate oxide film
212
and a polysilicon layer
213
are deposited on the entire SOI substrate. The polysilicon layer
213
and the gate oxide film
212
are successively etched using a photosensitive film
224
as a mask, and thereafter, the gate oxide film
212
and a gate electrode
214
are formed (FIGS.
12
B and
12
C). Subsequently, low-concentration impurity ions are implanted into the SOI layer
203
using the gate electrode
214
as a mask, forming an LDD region
215
(FIG.
12
D). Subsequently, oxide film spacers
216
and
216
are formed on both side wall sides of the gate electrode
214
, and finally high-concentration impurity ions are implanted using the gate electrode
214
and the oxide film spacers
216
as a mask, forming a source junction region
217
and a drain junction region
218
(FIG.
12
E).
(2) A Semiconductor Device Fabricating Method Using a LOCOS (Local Oxidation of Silicon) Process
FIGS. 14A through 14D
are process charts for explaining a semiconductor device fabricating method using a LOCOS process. First of all, as shown in
FIGS. 14A and 14B
, in the SOI substrate constructed of a silicon substrate
401
, an insulating layer
402
and a SOI layer
403
, the channel region is subjected to the LOCOS process, and thereafter, the resulting LOCOS oxide film is totally removed using a nitride film
405
as a mask, forming a recess. Subsequently, as shown in
FIG. 14C
, a gate oxide film
412
is formed, and thereafter, a polysilicon film
413
is deposited by the CVD (Chemical Vapor Deposition) method on the entire SOI substrate. Subsequently, the polysilicon film
413
is etched back to the surface of the nitride film
405
to form a gate electrode
414
. The nitride film is removed, and thereafter, a source junction region and a drain junction region are formed in the SOI layer
403
in a self-alignment manner using the gate electrode
414
as a mask.
In each of the transistors formed on the SOI layers fabricated by the prior art techniques shown in
FIGS. 12A through 12E
and
FIGS. 14A through 14D
, the portion where the channel region or the LDD region is formed is set at a specified depth, and the source junction region and the drain junction region can be made thick. Therefore, the transistors have the effect of reducing the resistances of the junction regions.
However, the transistors formed on the SOI layers fabricated by the semiconductor device fabricating method shown in
FIGS. 12A through 12E
and
FIGS. 14A through 14D
have the problems as follows.
The semiconductor device fabricating method (1) has the following problem.
According to the semiconductor device fabricating method shown in
FIGS. 12A through 12E
, the gate electrode
214
is formed by etching with the photosensitive film
224
used as a mask. The position of the photosensitive film
224
that serves as the mask formed through the processes of coating, exposure and developing varies within the range of accuracy of the exposure apparatus. Therefore, the photosensitive film
224
that serves as the mask can not always be formed at the center of the trench region
223
.
FIGS. 13A through 13D
are process charts when the position of the photosensitive film that serves as the mask is displaced. As shown in
FIG. 13A
, when a photosensitive film
324
is displaced from the center of the trench toward the source region side (leftward in FIGS.
3
A through
3
D), then a gate electrode
314
is formed (FIG.
13
B). As a result, in the next process for implanting low-concentration impurity ions into the LDD region, there is the structure in which an LDD region
315
a
located on the source side and an LDD region
315
b
located on the drain side become asymmetrical (FIG.
13
C). Next, when high-concentration impurity ions are implanted into a source junction region
317
and a drain junction region
318
, then the transistor comes to have a structure in which the source side and the drain side become asymmetrical about a channel region
319
(FIG.
13
D). The degree of asymmetry depends on the accuracy of the exposure apparatus, and the gate electrode cannot always be formed at the center of the trench region. For this reason, it is very difficult to form the gate electrode in the specified position with high reproducibility, and this consequently leads to the problem that the resulting transistors significantly vary in electrical characteristics.
As countermeasures against the above problem, when the trench width is increased so that the LDD regions become equivalent to each other on the source side and the drain side as shown in
FIG. 13E
, then the size of the transistor increases, resulting in a disadvantage in terms of integration. Furthermore, since a source junction region
325
and a drain junction region
326
located outside the LDD regions
315
a
and
315
b
are reduced in thickness, and therefore, the junction regions come to have a great resistance to reduce the
Fahmy Jr. Wael
Nixon & Vanderhye P.C.
Rao Shrinivas H.
Sharp Kabushiki Kaisha
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