Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-09-05
2004-06-22
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S062000, C326S081000, C326S083000, C326S056000, C327S333000
Reexamination Certificate
active
06753697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device which employs two or more power supply potentials, and more specifically to a semiconductor device which includes a level shift circuit transmitting a signal from a lower voltage power supply circuit to a high voltage power supply circuit.
2. Description of the Background Art
Recently, with the development of a microscopic processing technique for semiconductors, the number of transistors which can be integrated on one chip has surprisingly increased. At the same time, the restriction of voltage which can be applied to a transistor has become stricter. Further, it is inevitable to decrease a power supply potential so as to suppress the increase of consumption power following the increase of the number of transistors to be integrated. At present, in case of a MOS transistor which is used most widely, as a minimum processing dimension decreases to 0.25 &mgr;m, to 0.18 &mgr;m and to 0.15 &mgr;m, a power supply potential decreases to 2.5 V, to 1.8 V and to 1.5V, respectively. The power supply potentials is used in the core section of an integrated circuit and is, therefore, referred to as VDD.
Meanwhile, a power supply potential VDDH of an interface section which exchanges signals with other chips is set higher than that of the core section, irrespectively of the development of the processing technique. Normally, power supply potential VDDH is set at 3.3 V. A state-of-the-art transistor cannot be employed at a voltage of 3.3 V. Though the performance is considerably lower, a transistor is used at the interface section of which gate oxide film is intentionally made thicker than that of the transistor at the core section.
The reason of setting the power supply potential of the interface section high is as follows. Since all of semiconductor devices mounted on a printed wiring board are not manufactured by the state-of-the-art processing technique and many semiconductor devices still operate according to a conventional interface standard, the change of the interface standard brings about much confusion.
Furthermore, since the interface section is provided in proximity to an input/output pin, it is necessary to increase resistance against surge breakdown of the input/output pin caused by an electrostatic force. If the thickness of the gate oxide film of a transistor in the interface section is set large, the resistance of the semiconductor device advantageously increases.
As stated above, if two or more power supply potentials are employed, it is necessary to provide a level conversion circuit (level shift circuit) which shifts the amplitude of a signal potential among circuit blocks using the respective power supply potentials.
FIG. 20
is a circuit diagram for explaining level shift sections arranged in the connection section between two circuit blocks having different power supply potentials, respectively.
Referring to
FIG. 20
, a core section
502
is a circuit which receives power supply potential VDD as an operating power supply potential. Core section
502
includes a NAND circuit G
50
which receives signals D
0
and EN, an inverter
506
which receives and inverts the output of NAND circuit G
50
, an inverter
504
which receives and inverts signal EN, a NOR circuit G
51
which receives the output of inverter
504
and signal D
0
, and an inverter
508
which receives and inverts the output of NOR circuit G
51
.
An interface section
503
is a circuit which receives power supply potential VDDH as an operating power supply potential. Interface section
503
includes level shift circuits
513
and
515
, and a driving section
519
which drives an output node D
3
in accordance with data held in level shift circuits
513
and
515
.
Level shift circuit
513
includes a P-channel MOS transistor P
50
which is connected between a node applied with power supply potential VDDH and a node D
54
and which has a gate connected to a node D
51
, an N-channel MOS transistor N
50
which is connected between node D
54
and a ground node and which has a gate receiving the output of NAND circuit G
50
, a P-channel MOS transistor P
51
which is connected between the node applied with power supply potential VDDH and node D
51
and which has a gate connected to node D
54
, and an N-channel MOS transistor N
51
which is connected between node D
51
and the ground node and which has a gate receiving the output of inverter
506
.
Level shift circuit
515
includes a P-channel MOS transistor P
52
which is connected between a node applied with power supply potential VDDH and a node D
55
and which has a gate connected to a node D
52
, an N-channel MOS transistor N
52
which is connected between node D
55
and the ground node and which has a gate receiving the output of NOR circuit G
51
, a P-channel MOS transistor P
53
which is connected between the node applied with power supply potential VDDH and node D
52
and which has a gate connected to node D
55
, and an N-channel MOS transistor N
53
which is connected between node D
52
and the ground node and which has a gate receiving the output of inverter
508
.
Driving section
519
includes an inverter
520
which has an input connected to node D
51
, an inverter
522
which receives and inverts the output of inverter
520
, and a P-channel MOS transistor PD
1
which is connected between the node applied with power supply potential VDDH and output node D
3
and which has a gate receiving the output of inverter
522
.
Driving section
519
also includes an inverter
524
which has an input connected to node D
52
, an inverter
526
which receives and inverts the output of inverter
524
, and an N-channel MOS transistor ND
1
which is connected between output node D
3
and the ground node and which has a gate receiving the output of inverter
526
.
A level shift operation will be briefly described. Data is applied as signal D
0
from an internal circuit, not shown, included in core section
502
. If output enable signal EN is at H level, the data is outputted from output node D
3
to the outside of the chip.
If output enable signal EN is at L level, both of output transistors PD
1
and ND
1
are turned off and output node D
3
is set in a high impedance state.
A case where L level is outputted as the data from output node D
3
will be considered. In this case, output enable signal EN is set at H level (VDD) and data signal D
0
is set at L level (GND). Since the output of NAND circuit G
50
is at H level (VDD) on an output transistor PD
1
side, N-channel MOS transistor N
50
is turned on and N-channel MOS transistor N
51
is turned off. Accordingly, P-channel MOS transistor P
50
is turned off and P-channel MOS transistor P
51
is turned on. As a result, node D
54
of level shift circuit
513
is set at L level (GND) and node D
51
is set at H level (VDDH). Since the gate potential of output transistor PD
1
is at H level (VDDH), output transistor PD
1
is turned off.
On the other hand, since the output of NOR circuit G
51
is at H level (VDD) on an output transistor ND
1
side, N-channel MOS transistor N
52
is turned on and N-channel MOS transistor N
53
is turned off. Accordingly, P-channel MOS transistor P
52
is turned off and P-channel MOS transistor P
53
is turned on. As a result, node D
55
of level shift circuit
515
is set at L level (GND) and node D
52
thereof is set at H level (VDDH). The gate potential of output transistor ND
1
is at H level (VDDH) and output node D
3
is driven to L level (GND).
A case where H level is outputted as the data from output node D
3
will next be considered. In this case, output enable signal EN is set at H level (VDD) and data signal D
0
is also set at H level (VDD).
Since the output of NAND circuit G
50
is at L level (GND) on the output transistor PD
1
side, N-channel MOS transistor
50
is turned off and N-channel MOS transistor N
51
is turned on. Accordingly, P-channel MOS transistor P
50
is turned on and P-channel MOS transistor P
51
is turned off. As a result, node D
54
of level sh
McDermott & Will & Emery
Renesas Technology Corp.
Tan Vibol
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