Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2000-07-20
2001-07-03
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189060
Reexamination Certificate
active
06256236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of an input/output circuit for transmitting and receiving a signal between semiconductor devices.
2. Description of the Background Art
FIG. 5
is a block diagram showing a portion related to an input/output circuit of a conventional semiconductor device.
FIG. 5
illustrates as one example a circuit structure for exchanging data between a semiconductor memory device
2000
and a memory control device
2100
.
Semiconductor memory device
2000
includes an input circuit
1
for receiving an externally supplied control signal, a control circuit
5
for controlling an operation of semiconductor memory device
2000
according to a control signal supplied from input circuit
1
, a memory array
7
for storing externally supplied data, and an input/output circuit
3
for transmitting and receiving data to and from the outside of semiconductor memory device
2000
.
Memory control device
2100
includes an output circuit
2
for outputting a control signal, a control circuit
6
for generating a control signal, and an input/output circuit
4
for transmitting and receiving data to and from semiconductor memory device
2000
.
Output circuit
2
of memory control device
2100
supplies to input circuit
1
of semiconductor memory device
2000
control signals such as chip select signal CS, row address strobe signal RAS, column address strobe signal CAS, write enable signal WE, address signal Address and clock enable signal CKE.
Input data Din supplied from memory control device
2100
to semiconductor memory device
2000
as well as output data Dout from semiconductor memory device
2000
are applied to a data signal line.
FIG. 6
is a timing chart illustrating operations of conventional semiconductor memory device
2000
and memory control device
2100
shown in FIG.
5
.
Referring to
FIG. 6
, at time t
1
, “001” is supplied as a row address from memory control device
2100
to semiconductor memory device
2000
and signal ACT is activated (“L” level). Then, internal RAS signal operates to cause activation of a select line (word line) corresponding to an internal row “001” in memory array
7
. At time t
2
, data is written into a column address, “100.” When this writing operation is performed, data from a terminal Din of memory control device
2100
(memory tester, for example) is output to the data signal line to be supplied to semiconductor memory device
2000
.
After this, an instruction for reading from the same address is issued at time t
3
, and data is read from semiconductor memory device
2000
at time t
4
. When this reading operation is performed, data Dout from semiconductor memory device
2000
is output to the data signal line.
Further, precharge operation is done at time t
5
and then a self refresh mode starts at time t
6
in which an internal row address (internal Row) “010” indicated by an internal counter is refreshed.
FIG. 7
is a block diagram illustrating a structure of input/output circuits
3
and
4
shown in FIG.
5
.
Input/output circuit
3
includes an output buffer
30
operating between supply potential Vcc and ground potential Vss for supplying received signal Dout to a data input/output terminal and an input buffer
31
receiving supply potential Vcc and ground potential Vss to operate for receiving a signal from the input/output terminal and supplying the signal as internal data Din into semiconductor memory device
2000
.
Input/output circuit
4
includes an output buffer
32
receiving supply potential Vcc and ground potential Vss to operate for receiving data Din generated from control circuit
6
and supplying the data to semiconductor memory device
2000
via a data input/output terminal and a data signal line and an input buffer
33
receiving supply potential Vcc and ground potential Vss to operate for receiving a signal from the data input/output terminal and supplying the signal to control circuit
6
.
Output buffers
30
and
32
and input buffers
31
and
33
illustrated in
FIG. 7
are all inverter circuits.
FIG. 8
is a timing chart illustrating operations of input/output circuits
3
and
4
shown in FIG.
7
.
Referring to
FIG. 8
, at time t
0
, output buffer
30
of input/output circuit
3
is in a high-impedance state and output buffer
32
of input/output circuit
4
outputs data of “H” level (supply potential Vcc level). In this case, the potential level of the data signal line is “H” level and the level of internal data Din supplied from input buffer
31
in input/output circuit
3
is “L” level which is an inverted version of the data signal line level.
At time t
1
, a signal of “L” level is supplied from output buffer
32
to the data signal line and this level is inverted by input buffer
31
to change the level of internal data Din to “H” level.
At time t
2
, output buffer
32
enters a high-impedance state while output buffer
30
stays in the high-impedance state. As long as the potential of the data signal line is kept at “L” level, internal data Din is maintained at “H” level.
At time t
3
, output buffer
32
still stays in the high-impedance state and output buffer
30
outputs “H” level. Then, the level of the data signal line attains “H” level and the level of internal data Din changes to “L” level.
At time t
4
, the output level of output buffer
30
changes to “L” level and accordingly the level of the data signal line and the level of internal data Din change to “L” and “H” levels respectively.
As understood from the above, when data is transmitted between input/output circuits
3
and
4
, output buffer
30
should be maintained in the high-impedance state at least during the period in which data is output from output buffer
32
, while output buffer
32
should be maintained in the high-impedance state during the period in which data is output from output buffer
30
.
In other words, it is impossible to simultaneously output data from output buffer
30
and output buffer
32
onto the data signal line.
According to the method of operation described above, data cannot be input to semiconductor memory device
2000
during the period in which semiconductor memory device
2000
outputs data.
Further, after a self refresh mode starts, internal RAS which is automatically generated within the semiconductor memory device operates asynchronously relative to an external signal. A select line (word line) to be activated is determined by an address indicated by an internal counter.
Therefore, conventional semiconductor memory device
2000
does not have means for monitoring from the outside a signal which is generated within the device.
A problem further arises that any abnormal state of an internal signal such as an abnormally prolonged cycle of self refresh is difficult to detect.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device to and from which data can be input and output simultaneously from and to the same terminal.
In order to achieve this object, a semiconductor device according to one aspect of the present invention includes therein, for the purpose of allowing signals to be input and output simultaneously from and to the same terminal, a circuit for clamping the potential of an input signal which is supplied from the outside, and the level of clamping this input signal is controlled according to an internal signal. In this way, the level of the internal signal can be output to the outside by using variation of the clamping level of the input signal potential.
Specifically, the present invention is a semiconductor device including an internal circuit and an input/output circuit.
The internal circuit operates according to a signal supplied from the outside of the semiconductor device, and generates an internal signal having a first logic value and a second logic value. The input/output circuit transmits a signal between the internal circuit and the outside of the semiconductor device. The input/output circuit includes a signal terminal, a first input circuit, a first potentia
Ho Hoai V.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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