Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2001-06-08
2002-07-02
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C327S534000, C327S536000
Reexamination Certificate
active
06414881
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device for generating internal voltage through pumping operation. Specifically, the present invention relates to a substrate bias voltage generating circuit for generating bias voltage to be applied to a substrate region.
2. Description of the Background Art
A semiconductor device is provided with an internal voltage generating circuit in order to reduce power consumption of a whole system and to generate a voltage at a desired level. Internal voltage is classified into a high voltage higher than an external power supply voltage, a reference voltage at a level between the ground voltage and the power supply voltage, a negative bias voltage applied to a substrate region of the semiconductor device, and so on. Particularly in a semiconductor memory device, a bias voltage VBB is applied to the substrate region in order to stabilize the threshold voltage of memory cell transistors composed of MOS transistors (insulated gate type field effect transistors) and to reduce the junction capacitance thereof.
FIG. 14
is a block diagram schematically showing a conventional bias voltage generating circuit. In
FIG. 14
, the bias voltage generating circuit includes an active bias voltage generating circuit activated in an active cycle
102
for generating the bias voltage VBB, a standby bias voltage generating circuit
104
for generating the bias voltage VBB in a standby cycle, and a level detecting circuit
100
for detecting whether or not the level of the bias voltage VBB reaches a predetermined voltage level to selectively activate, according to the detection result, the active bias voltage generating circuit
102
or the standby bias voltage generating circuit
104
. This level detecting circuit
100
includes a level detector for the active cycles and a level detector for the standby cycles, which generate active activity control signal &phgr;AL and standby activity control signal &phgr;SL, respectively. The bias voltage VBB is a negative voltage. If this bias voltage VBB drops below a predetermined value, the level detecting circuit
100
stops the bias voltage generating operation of the bias voltage generating circuit(s)
102
and/or
104
.
The active bias voltage generating circuit
102
has a large charge supply capability and prevents fluctuation in the level of the bias voltage VBB in the operation of an internal circuit in an active cycle. The standby bias voltage generating circuit
104
has a relatively small charge supply capability, and suppresses fluctuation in the bias voltage VBB due to a leakage current in a standby state.
The active bias voltage generating circuit
102
includes an active ring oscillator
102
a
that performs oscillation operation selectively, dependently on the activity control signal &phgr;AL from the level detecting circuit
100
, and an active pumping circuit
102
b
that utilizes a charge pumping operation of a capacitor and supplies charges to an output node, dependently on an oscillation signal from the active ring oscillator
102
a
. When the activity control signal &phgr;AL is in an active state and instructs that the bias voltage VBB does not reach a predetermined voltage level, the active ring oscillator
102
a
performs oscillation operation. When the bias voltage VBB reaches the predetermined level, the oscillator
102
a
stops the oscillation operation.
The standby bias voltage generating circuit
104
includes a standby ring oscillator
104
a
that performs oscillation operation selectively, dependently on the activity control signal &phgr;SL from the level detecting circuit
100
, and a standby pumping circuit
104
b
that performs a charge pumping operation through a capacitor and generates the bias voltage VBB, dependently on an oscillation signal from the standby ring oscillator
104
a
. When the activity control signal &phgr;SL instructs that the bias voltage VBB does not reach a predetermined voltage level, the standby ring oscillator
104
a
also performs oscillation operation. When the activity control signal &phgr;SL instructs that the bias voltage VBB reaches the predetermined level, the oscillator
104
a
stops the oscillation operation.
By providing a bias voltage generating circuit for each of an active cycle and a standby cycle, the operation of the active bias voltage generating circuit
102
, which has a large charge supply capability, is stopped in a standby cycle to reduce power consumption. The active pumping circuit
102
b
and the standby pumping circuit
104
b
utilize charge pumping operation of capacitors. The capacitance values of these capacitors are different from each other and the charge supply capability of the standby pumping circuit
104
b
is made smaller. In the charge pumping circuit utilizing the charge pumping operation of a capacitor, its charge supply capability is proportional to the frequency of an oscillation signal and the capacitance of the capacitor that performs the charge pumping operation.
A charge pumping circuit utilizing a capacitor can be formed into various structures. Typical examples of the charge pumping circuit. structure are a single boost type charge pumping circuit and a double boost type charge pumping circuit.
FIG. 15
is a block diagram showing a conventional single boost type charge pumping circuit. In
FIG. 15
, the single boost type charge pumping circuit includes: an inverter circuit IV
1
receiving a clock signal CLK from a ring oscillator; a delay circuit DL
1
for delaying an output signal of the inverter circuit IV
1
; a delay circuit DL
2
for delaying an output signal of the delay circuit DL
1
further; a NOR gate NG
1
receiving output signals of the delay circuits DL
1
and DL
2
; a NAND circuit NG
2
receiving the output signal of the inverter circuit IV
1
and the. output signal of the delay circuit DL
2
; a NOR gate NG
3
receiving the output signals of the inverter circuit IV
1
and the delay circuit DL
1
; a delay circuit DL
3
for delaying the output signal of the NOR gate NG
1
; a buffer circuit DL
4
for delaying the output signal of the NAND circuit NG
2
; an inverter IV
2
for inverting the output signal of the NOR gate NG
3
; a capacitor Clhavingone electrode node coupled to receive the output signal of the delay circuit DL
3
; a capacitor C
2
having one electrode node coupled to receive the output signal of the delay circuit DL
4
; a capacitor C
3
having one electrode node coupled to receive an output signal of the inverter circuit IV
2
; a P channel MOS transistor Q
1
connected between the other electrode node (node NF) of the capacitor C
3
and the ground node; P channel MOS transistors Q
2
and Q
3
connected in series between the node NF and the ground node; a P channel MOS transistor Q
4
connected between the other electrode node (node NB) of the capacitor C
1
and the ground node and having a gate connected to the node NF; a P channel MOS transistor Q
5
connected between the other electrode node (node NE) of the capacitor C
2
and the ground node and having a gate connected to the node NF; and a P channel MOS transistor Q
6
made conductive selectively, depending on the voltage level of the node NE, to transfer charges between the nodes ND and NO.
P channel MOS transistor Q
1
has a gate connected to the ground node so that the transistor Q
1
operates in a diode mode to damp the voltage level of the node NF to an absolute value Vthp of its threshold voltage. The MOS transistors Q
2
and Q
3
each are diode-connected in the forward direction from the ground node to the node NF, so that the voltage level of the node NF is damped on −2·Vthp, wherein Vthp represents the absolute value of the threshold voltage of each of Q
1
to Q
3
. Now, the description will be made of the operation of the single boost type charge pumping circuit shown in FIG.
15
.
Suppose such initial state that nodes NA-NF are at a level of the ground voltage Vss (=0V) and the clock signal CLK rises up to an H le
Akiyama Mihoko
Fujii Nobuyuki
Kobayashi Mako
Morishita Fukashi
Taito Yasuhiko
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
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