Semiconductor device capable of adjusting output impedance...

Details Semiconductor device capable of adjusting output impedance... Semiconductor device capable of adjusting output impedance...

2007-06-21

2009-02-10

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000

Reexamination Certificate

active

07489160

ABSTRACT:
In a semiconductor device capable of adjusting an output impedance of a first output impedance adjustable output buffer of an external semiconductor device connectable to the semiconductor device, a second output impedance adjustable output buffer is provided. A comparator compares a first output voltage of a real load circuit including the first output impedance adjustable output buffer with a second output voltage of a replica load circuit including the second output impedance adjustable output buffer. An output impedance control circuit transmits an output signal of the comparator to the external semiconductor device to adjust the output impedance of the first output impedance adjustable output buffer, so that the first output voltage is made equal to the second output voltage.

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patent: 2007/0290712 (2007-12-01), Gomez et al.
patent: 11-17518 (1999-01-01), None
JEDEC Solid State Technoloty Association, “JEDEC Standard DDR2 SDRAM Specification” JESD79-2A, Jan. 2004.

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