Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-10-23
2003-03-11
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S226000
Reexamination Certificate
active
06532183
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device comprising an internal potential generation circuit capable of adjusting an output potential.
2. Description of the Prior Art
In general, a semiconductor integrated circuit device is provided with an internal power supply potential generation circuit generating an internal power supply potential lower than an external power supply potential and supplying the internal power supply potential to an internal circuit. The output potential from the internal power supply potential generation circuit, dispersed by fluctuation of a fabrication process or the like, is adjustable.
In general, however, an external tester monitors the output potential of the internal power supply generation circuit for adjusting the same, and hence the output potential cannot be readily adjusted.
SUMMARY OF THE INVENTION
Accordingly, a principal object of the present invention is to provide a semiconductor device capable of readily adjusting the internal potential thereof.
The semiconductor device according to the present invention is provided with an internal potential generation circuit receiving a first level set signal including information indicating the level of an internal potential and generating an internal potential of a level responsive to the first level set signal, a signal generation circuit sequentially supplying a plurality of second level set signals one by one as the first level set signal, to the internal potential generation circuit and making the internal potential generation circuit generate a plurality of internal potentials of levels different from each other in a tuning mode for tuning the internal potential, and a compare circuit comparing each internal potential generated in the internal potential generation circuit with a reference potential and outputting a signal of a level responsive to the result of comparison in the tuning mode. Therefore, the second level set signal for generating an internal potential substantially equal to the reference potential can be readily detected on the basis of the signal output from the compare circuit, for readily adjusting the internal potential on the basis of the result of detection.
Preferably, the semiconductor device is further provided with a memory circuit for storing the signal output from the compare circuit. In this case, the signal output from the compare circuit can be temporarily stored in the memory circuit to be thereafter read, whereby the internal potential can be further readily adjusted.
Preferably, the semiconductor device is further provided with a detection circuit detecting the second level set signal for generating an internal potential substantially equal to the reference potential on the basis of the signal output from the compare circuit and a memory circuit for storing the second level set signal detected by the detection circuit. In this case, the semiconductor device itself detects the optimum second level set signal, which in turn can be read from the memory circuit, whereby the internal potential can be further readily adjusted.
Preferably, the compare circuit outputs a signal of a first or second level in response to whether the internal potential generated in the internal potential generation circuit is higher or lower than the reference potential, and the detection circuit includes a logic circuit outputting an activation signal in response to change of the level of the signal output from the compare circuit and a gate circuit receiving the second level set signals generated in the signal generation circuit and supplying the second level set signal to the memory circuit in response to the activation signal output from the logic circuit. In this case, the detection circuit can be readily formed.
Preferably, the semiconductor device is further provided with an internal circuit receiving the internal potential generated in the internal potential generation circuit and performing a prescribed operation, a plurality of signal terminals for transferring signals between the internal circuit and an external world and a scan path circuit connected between two predetermined signal terminals among the plurality of signal terminals for testing the internal circuit, and an output signal from the memory circuit is output to the external world through the scan path circuit. In this case, no individual output terminal for the memory circuit may be provided and hence the number of external terminals can be reduced.
Preferably, the semiconductor device is further provided with a program circuit including at least one fuse for generating a third level set signal including information indicating the level of the internal potential on the basis of whether or not the fuse is blown and a switching circuit supplying the second level set signal generated in the signal generation circuit as the first level set signal to the internal potential generation circuit in the tuning mode while supplying the third level set signal generated in the program circuit as the first level set signal to the internal potential generation circuit in a general operation. In this case, the fuse of the program circuit can be blown on the basis of the result of detection in the tuning mode, for readily adjusting and setting the internal potential.
Preferably, the semiconductor device is further provided with a blowing circuit blowing the fuse of the program circuit so that the program circuit outputs the third level set signal including the same information as the second level set signal stored in the memory circuit in addition to the program circuit and the switching circuit. In this case, the semiconductor device itself blows the fuse of the program circuit, whereby the internal potential can be readily adjusted and set.
Preferably, the semiconductor device operates in synchronization with an external clock signal and further comprises a frequency dividing circuit dividing the frequency of the external clock signal and outputting an internal clock signal, the signal generation circuit operates in synchronization with the internal clock signal and sequentially supplies the plurality of second level set signals one by one as the first level set signal to the internal potential generation circuit in a predetermined cycle, and the compare circuit compares each internal potential with the reference potential when a predetermined time elapses after the signal generation circuit supplies the second level set signal as the first level set signal to the internal potential generation circuit. In this case, the internal potential can be reliably temporarily set and compared.
Preferably, the semiconductor device is further provided with a voltage dividing circuit for dividing an external power supply voltage and generating the reference potential. In this case, a plurality of stages of reference potentials can be generated by changing the external power supply voltage in a plurality of stages.
Preferably, the internal potential generation circuit includes a constant current source connected between a line of an external power supply potential and a prescribed node, a variable resistance circuit, connected between the prescribed node and a line of a ground potential, having a resistance value varying with the first level set signal, a transistor connected between the line of the external power supply potential and a line of the internal potential and a control circuit controlling input voltage of the transistor so that the internal potential matches with the potential of the prescribed node. In this case, the internal potential generation circuit can be readily formed.
Preferably, a plurality of internal potential generation circuits and a plurality of compare circuits are provided, the plurality of internal potential generation circuits generate internal potentials of levels different from each other in response to the same first level set signal, each compare circuit receives a reference potential
Lebentritt Michael S.
McDermott & Will & Emery
Phung Ann
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