Semiconductor device and yield calculation method

Details Semiconductor device and yield calculation method Semiconductor device and yield calculation method

2011-01-11

2011-01-11

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07870520

ABSTRACT:
A semiconductor device yield calculation method and a computer program that include selecting from a designed device pattern a specified first pattern and a second pattern that differs from the first pattern, finding a probability that the second pattern passes a test when the first pattern passes the test for each of a plurality of distances between the first pattern and the second pattern, and finding a yield of the device pattern based on a product of the probability and a yield value for the first pattern.

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Jitendra Khare et al. Accurate Estimation of Defect-Related Yield Loss in Reconfigurable VLSI Circuits; IEEE Journal of Solid-State Circuits. vol. 28, No. 2, Feb. 1993, pp. 146-156.

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