Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-03-10
2001-09-18
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S653000
Reexamination Certificate
active
06291834
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-068071, filed Mar. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a testing method therefor. More specifically, the present invention relates to the structure of portion of a semiconductor substrate that is subject to stress and a testing method for detecting damage to that portion. The present invention is adapted to detect damage that occurs within the substrate of a semiconductor chip which is subject to mechanical stress when it is packaged into a casing.
In recent years, as integrated circuits advance in miniaturization of chip design rules and functionality, the margin of manufacture generally tends to decline. In particular, the periphery of bonding pads is directly subjected to mechanical shocks by the bonder during the bonding step after a semiconductor chip is placed in a casing. Depending on the material and structure of the semiconductor chip, cracks may be induced in the chip immediately below the bonding pads.
FIG. 1
is a fragmentary plan view illustrating an arrangement of bonding pads of a conventional LSI chip and
FIG. 2
is a sectional view illustrating the occurrence of a crack immediately below a pad.
In
FIG. 1
,
81
denotes an internal circuit area of the LSI chip,
82
a peripheral area (input/output area) of the chip, and
83
an area where the pads are arranged.
In
FIG. 2
,
90
denotes a semiconductor substrate,
92
a field oxide film,
92
an interlayer insulating film,
93
a pad formed on the interlayer insulating film,
94
a passivation film, and
95
a crack.
The operating speed of MOS devices shows a tendency to have reached the top because of an increase in parasitic resistance due to shallow source-drain junctions and velocity saturation of carriers. As a countermeasure, an attempt has been made to use low-resistivity Cu interconnections and low-dielectric-constant interlayer insulating films.
It has been reported that, when a low-dielectric-constant interlayer insulating film is used, a failure of Cu interconnections peeling off the insulating film occurs immediately below the pads (Mukul Saran et al., “Elimination of Bond-Pad Damage Through Structural Reinforcement of Intermetal Dielectrics”, Proceedings of International Reliability Physics Symposium, 1998, pp. 225 to 231). This failure is a serious problem for the evolution of LSIs.
Heretofore, in order to detect damage that occurred in the substrate below pads, it has been required to disassemble the semiconductor chip and etch the substrate using an etchant such as KOH. With this method, however, a troublesome defect detection processing is needed and it is impossible to detect accurately substrate damage over the whole region of the chip.
BRIEF SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which permits damage to that region of a semiconductor substrate which is subjected to mechanical stress to be detected accurately and easily and a testing method therefor.
According to a first aspect of the present invention there is provided a semiconductor device comprising: a semiconductor substrate having an area where a circuit is formed; and a region of a PN junction formed in the circuit-formed area of the semiconductor substrate so that a P-type semiconductor region and an N-type semiconductor region meet vertically with respect to a surface of the semiconductor substrate, a given reverse bias voltage being applied across the PN junction to test the PN junction region for defects.
The PN junction is preferably formed such that each of the P-type semiconductor region and the N-type semiconductor region is formed in a shape of a comb and fingers of the comb-shaped P-type semiconductor region are interleaved with those of the comb-shaped N-type semiconductor region.
Each of the P-type semiconductor region and the N-type semiconductor region has a finger width and impurity concentration thereof preferably set so that each portion of the semiconductor substrate that corresponds to a respective one of the fingers of the P-type and the N-type semiconductor region becomes completely depleted when the given reverse bias voltage is applied across the PN junction.
The PN junction region is preferably formed in a form of a strip along a substantial interface direction of the P-type and the N-type semiconductor region.
The semiconductor device preferably further comprises a plurality of bonding pads and the PN junction region in the strip form is preferably located below the plurality of bonding pads.
The semiconductor device preferably further comprises, at one end of the PN junction region in the strip form, a first testing pad connected to the P-type semiconductor region and a second testing pad connected to the N-type semiconductor region.
The fist and second testing pads are preferably provided in a pad area where the plurality of bonding pads are placed.
The PN junction region in the strip form is preferably formed on a periphery of the circuit-formed area of the semiconductor substrate.
According to a second aspect of the present invention there is provided a semiconductor device comprising: a semiconductor substrate; a plurality of bonding pads formed on the semiconductor substrate; and a plurality of PN junction regions each of which is formed in the semiconductor substrate immediately below at least a central portion of a respective one of the plurality of bonding pads, each of the PN junction regions being formed such that a P-type semiconductor region and an N-type semiconductor region meet vertically with respect to a surface of the semiconductor substrate and the plurality of PN junction regions being electrically connected in parallel.
The P-type semiconductor region and the N-type semiconductor region in an arbitrary one of the plurality of PN junction regions are preferably formed continuous with the P-type semiconductor region and the N-type semiconductor region, respectively, in an adjacent one of the arbitrary one of the plurality of PN junction regions.
A reverse voltage smaller in magnitude than an inherent breakdown voltage of a PN junction is applied across the PN junction of each of the plurality of PN junction regions.
Each of the P-type semiconductor region and the N-type semiconductor region has a size and impurity concentration thereof preferably set so as to be completely depleted when a given reverse bias voltage smaller in magnitude than an inherent breakdown voltage of a PN junction formed thereby is applied therebetween.
The PN junction region is preferably formed such that each of the P-type semiconductor region and the N-type semiconductor region is formed in a shape of a comb and fingers of one of the comb-shaped P- and N-type semiconductor regions are interleaved with those of the other.
The semiconductor device preferably further comprises electrode pads electrically connected to the P-type semiconductor region and the N-type semiconductor region, respectively, through which a reverse voltage is applied between the P-type semiconductor region and the N-type semiconductor region.
The electrode pads are preferably provided in a pad area where the plurality of bonding pads are placed.
The semiconductor device preferably further comprises an in-chip test circuit which applies a given reverse voltage between the P-type semiconductor region and the N-type semiconductor region.
As an alternative, a given voltage may be externally applied across the PN junction through electrode pads.
According to a third aspect of the present invention there is provided a semiconductor device testing method comprising the steps of: preparing a semiconductor chip having a PN junction formed in a semiconductor substrate immediately below at least a central portion of each of bonding pads, the PN junction being formed of a P-type semiconductor region and an N-type se
Foley & Lardner
Kabushiki Kaisha Toshiba
Ngo Ngan V.
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