Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-03-30
2008-03-18
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S764000, C714S785000, C714S804000, C714S810000, C714S819000, C714S718000, C714S723000, C365S201000
Reexamination Certificate
active
07346829
ABSTRACT:
A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.
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Ito Yutaka
Riho Yoshiro
Elpida Memory Inc.
Trimmings John P
Young & Thompson
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