Semiconductor device and storage cell having multiple latch...

Details Semiconductor device and storage cell having multiple latch... Semiconductor device and storage cell having multiple latch...

2006-03-31

2009-10-13

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S118000, C365S049130, C365S051000, C365S052000, C365S063000, C365S154000, C365S189050, C365S230060

Reexamination Certificate

active

07603510

ABSTRACT:
A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.

REFERENCES:
patent: 5602797 (1997-02-01), Kang
patent: 2007/0133314 (2007-06-01), Chae
patent: 04090196 (1992-03-01), None
patent: 10-335992 (1998-12-01), None

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