Semiconductor device and skew adjusting method

Details Semiconductor device and skew adjusting method Semiconductor device and skew adjusting method

2007-04-17

2007-04-17

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S232000, C365S236000, C713S500000, C713S502000, C713S503000

Reexamination Certificate

active

11260199

ABSTRACT:
Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

REFERENCES:
patent: 5995441 (1999-11-01), Kato et al.
patent: 6489819 (2002-12-01), Kono et al.
patent: 6915443 (2005-07-01), McBride et al.
patent: 2003/0226055 (2003-12-01), Yoshitake
patent: 2003-271447 (2003-09-01), None

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