Semiconductor device and semiconductor module using the same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip

Reexamination Certificate

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C257S723000, C257S686000, C257S737000, C257S738000

Reexamination Certificate

active

06617695

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to low-profile semiconductor devices which can be packaged with high density and a semiconductor module using them, and more particularly to a semiconductor device which can improve heat-cycle resistant characteristic and effectively prevent short-circuiting between solder bumps for packaging and a semiconductor module using them.
Previously known semiconductor modules include SIMMs (Single Memory Module) and DIMMs (Dual Inline Module). The SIMM is a storage module in which a plurality of plastic package ICs are mounted on a single surface of a glass-epoxy substrate, and each of the plastic packaged ICs has an external lead protruding from the side of an IC package body resin-sealed in an epoxy resin. The DIMM is a storage module in which a plurality of the same plastic packaged ICs are mounted on both surfaces of the glass epoxy substrate.
FIG. 13
is a plan view of a conventional semiconductor device, and
FIG. 14
is a side view of FIG.
13
. In
FIGS. 13 and 14
, reference numeral
1
denotes a substrate including substrates
1
a
,
1
b
, and
1
c
which are spaced apart from one another. Each substrate component has lands
3
for mounting an IC package
7
on both upper and lower surfaces. The substrate component has also lands
4
outside the lands
3
. The lands
4
serve as terminals for external connection. The corresponding lands
3
and
4
are electrically connected to each other by wirings
5
on both surfaces of the substrate
1
. The lands
4
for external connection on both surfaces of the substrate
1
are connected to each other by conductors embedded in through-holes.
A solder bump
6
, located at the tip of the land
4
for making an external connection on the one surface of the substrate
1
(lower side in FIG.
14
). The IC package
7
includes a package body
8
and straight leads
9
which protrude laterally from both right and left sides of the body
8
. The straight leads
9
are electrically connected to the corresponding lands
3
for mounting and supported by the substrate
1
. Reference numeral
2
denotes a gap between the substrate
1
(
1
a
,
1
b
,
1
c
) and the package body
8
. In this way, a semiconductor device
24
includes the substrate
1
, lands
3
for mounting, lands
4
for external connection, wirings
5
, solder bumps
6
and IC package
7
.
The semiconductor device
24
can be manufactured as follows. First, with the IC package
7
positioned on the upper surface of the substrate
1
, the straight leads
9
are soldered to the lands
3
for mounting by a re-flow technique. Next, the substrate
1
is turned upside down. Likewise, on the lower surface of the substrate
1
, the straight leads
9
of another IC package
7
are soldered to the lands
3
for mounting, and the solder bumps
6
are soldered to the tips of the land
4
for external connection.
The structure of a semiconductor module will be explained.
FIG. 15
is a side view of the structure of a conventional semiconductor module in which a plurality of semiconductor devices one of which is shown in
FIGS. 13 and 14
, are soldered on a mother board
20
. As seen from
FIG. 15
, lands
21
for mounting the semiconductor device
24
are formed on the upper surface of the mother board
20
. The solder bumps
6
are electrically connected to the semiconductor device
24
, respectively. Likewise, the solder bumps
6
of another semiconductor device
24
are electrically connected to the lands
21
on the lower surface of the mother board
20
. In this way, a semiconductor module
25
includes the mother board
20
, upper and lower lands
21
and semiconductor devices
24
.
The semiconductor module
25
can be manufactured as follows. First, a semiconductor device
24
is positioned on the upper side of the mother board
20
. In this case, solder paste is previously supplied to contact positions between the solder bumps
6
and the lands
21
. The solder paste and solder bumps
6
are melted and bonded to the lands
21
so that the semiconductor device
24
is secured to the mother board
24
. Next, the mother board
20
is turned upside down. Likewise, another semiconductor device
24
positioned on the lower side of the mother board
20
is secured to the mother board
20
. Thus, the semiconductor module
25
is completed.
The upper semiconductor device
24
which is first soldered and secured to the mother board
20
and is shown at the lower position in
FIG. 15
is caused to “reflow” in its dangling state. Therefore, the solder bumps
6
are extended downward owing to the weight of the semiconductor device itself so that they are deformed in a “tsuzumi” (hand drum) shape with its diameter decreasing toward center. On the other hand, the upper semiconductor device
24
which is afterward, soldered and secured to the mother board
20
and is shown at the upper position in
FIG. 15
is caused to reflow in a state placed on the mother board
20
. Therefore, the solder bumps
6
are compressed owing to the weight of the semiconductor device itself so that they become deformed in a barrel shape with its diameter increasing toward center.
FIG. 16
is a schematic side view of the solder bumps
6
thus deformed on the upper and lower surfaces of the semiconductor module
25
. If the upper solder bumps are crushed as seen from
FIG. 16
so that they are going to swell in diameter from the prescribed positions together with the paste, the solder bumps
6
may be short-circuited to each other at the time of reflow, provided that the bonding pitch between the adjacent solder bumps
6
is small.
The lower solder bump
6
, as seen from
FIG. 16
, becomes deformed into the “tsuzumi” shape during its reflow so that the sectional area of the bonding portion is going to decrease. Therefore, when the completed semiconductor module
25
is subjected to the temperature cycle test in which a temperature change from −40° C. to 125° C. is made every thirty minutes, the soldered portion may be broken owing to a crack due to thermal fatigue. The breakage due to the thermal fatigue is likely to occur at the region where the maximum bending moment due to thermal deformation is applied to the bonding end of the solder bump, i.e. the bonding boundary between the land
4
for external connection having a small sectional area and the solder bump
6
. However, the usable solder bump
6
must have a small diameter under the limitation of the pitch between the adjacent leads. Therefore, breakage may occur at the portion having a small secondary moment at the sectional area of the bonding boundary, i.e., having a small sectional area at the bonding boundary.
On the other hand, the semiconductor module
25
incorporates the mother boards
20
having different thermal expansion coefficients, substrates
1
, IC packages
7
and circuit components (not shown).
Therefore, thermal deformation occur at the soldering portion owing to a temperature change during the operation or during the temperature cycle test. The quantity of the thermal deformation is proportional to the difference between the different thermal expansion coefficients, distance and temperature difference between the soldering portions. The largest thermal deformation occurs at the soldering portions of the lands
4
for external connection corresponding to the lands
3
for mounting at both ends which are secured by soldering and interpose the longest distance therebetween. The breakage may occur at the soldering portions of these both ends.
The holding strength with N solder bumps
6
aligned in a row on both sides of the IC package
7
, when the IC package
7
is bonded to the substrate
1
can be represented as follows. In this case, the solder bump
6
is approximated as a cylinder having a diameter D. Assuming that the permissible stress of solder at the temperature of reflow, e.g., about 200° C. is &sgr;a and the permissible holding weight of the entire solder cylinder of the solder bump
6
is Wa, Wa=&sgr;a×&pgr;×D×D×2×N/4. From this equa

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