Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-06-19
2003-03-25
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C714S718000, C714S719000, C714S720000
Reexamination Certificate
active
06539324
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method for testing a semiconductor device, and in particular to a semiconductor device and a semiconductor device testing method that together provide an effective means for efficiently testing a content addressable memory (CAM) cell, a word matching circuit and a priority encoder.
2. Background of the Invention
A content addressable memory (CAM) has a function for the entry of reference data, and the output of an address whereat data are recorded that match the reference data. Of course, the CAM also has the same memory functions as a common memory device for selecting the address of a memory cell and to write data thereto or to read data therefrom.
The data search function is carried out using a reference data line provided for the CAM, and a search result output line for outputting the result obtained from a comparison of the reference data and the stored data. The reference data and the stored data are compared bit by bit at every word along the word line corresponding to every address. Subsequently, the comparison results are transferred to the search result output line, whereby they are transmitted to a word matching circuit. When the data for all the word bits, or if there are masked word bits, the data for word bits that are not masked, have been matched, a matching flag is output to the output terminal of the word matching circuit provided for each word line. The address of the word line whereat the matching flag is set is output by a priority encoder. When a plurality of words are matched, the priority encoder determines the priority order, and outputs the address having the highest priority. For determination of the priority order, for example, the highest priority is allocated to the address having the smallest address number.
It should be noted that content addressable memory is described, for example, in the “LSI Handbook”, Institute of Electronic Communication, by Ohm Co., Ltd., Nov. 30, 1984, pp. 523-525.
When such a CAM is manufactured, the storage and reading operation for the memory cell must be tested to determine whether it is correct, and the operation of the word matching circuit and the priority encoder, i.e., the search function, must also be tested to determine whether it is correct. The testing can be conducted as follows. Test data are written to a CAM array at a designated test address which is employed as reference data to perform a search. The search address that is output is compared to the test address to determine the correctness of the search operation.
As previously described, when there are a plurality of words that match the reference data, the priority encoder outputs one search result (searched address) in accordance with the priority order. Therefore, the testing step must include the following conditions: (1) the same data as the test data should not be stored at an address having a higher priority than the test address; and (2) when the address to be tested is other than an address having the lowest priority, the same data as the test data should be stored in at least one address having a lower priority than the test address.
When the same data as the test data are recorded at the address having the higher priorities, the address whereat the data are recorded is output as the search result. Even when the CAM is operated correctly, the test addresses do not match the searched addresses, and the correctness of the operation of the CAM can not be determined. Condition (1) is required in order to avoid this occurrence. If condition (2) is not satisfied even when condition (1) has been established, it can be determined whether an address having a high priority has been correctly selected among the addresses whereat the data match.
A test is conducted for all the addresses while taking the above conditions into account. When an address that matches a test address is correctly output for all addresses, the correctness of the CAM is confirmed.
Assuming that the test is begun with the address having the highest priority defined by the priority encoder and is continued using addresses having lower priorities, the following problem arises. In order to establish the above conditions, the data stored at the preceding test address must be rewritten into the background data (or data different from the test data), and the same data as the test data must be written to the address following the test address having lower priorities. This operation is not preferred because the number of test steps for each address is increased. Further, while taking into account the fact that the search function is mounted in a built-in self test circuit on the chip of the semiconductor device, the number of circuits is increased, and accordingly, the chip size or the power consumption is increased.
It is, therefore, one object of the present invention to eliminate a redundant test step during the process for testing the search function of a CAM having a priority encoder.
It is another object of the present invention to employ the minimum number of steps to detect a failure in a memory cell or a word matching circuit, and to also detect the failure of a priority encoder function.
BRIEF SUMMARY OF THE INVENTION
Summary of the Invention
An overview of the present invention will now be described. According to a semiconductor device testing method and a semiconductor device for the invention, a content addressable memory cell, a word matching circuit and a priority encoder are tested beginning at an address having the lowest priority as defined by the priority encoder.
According to this testing method, background data that differ from test data are written before the test is conducted, and the test data are written to the address, a test address, having the lowest priority. Since background data are previously written to the addresses having higher priorities, during the search operation the address whereat the test data are written (the address having the lowest priority) should be output as a search address. The search address should match the test address as long as the CAM is operated correctly.
Then, an address having the second lowest priority is generated, and the test data are written to this address as a test address, while the data at the preceding address that was tested are unchanged. Therefore, at this time, the test data are stored at the addresses having the lowest and the second lowest priorities, and the background data are stored at the other addresses. Under these conditions, the search operation is performed using the test data as reference data. As is described above, since the matching address having the highest priority must be the current test address, the test address should be output as a result of the search, and the test address should match the search address (the output address serving as the search result) so long as the CAM is operated correctly. This testing operation is repeated by designating an address having a higher priority until the testing of all the remaining addresses has been completed.
According to this testing method, the data that were previously tested are not affected. That is, no data deletion or data writing operation is performed for the data, and the same data as the test data are not written to an untested address. In other words, the data writing operation is performed for each address only once. As a result, the number of test steps can be minimized.
Furthermore, according to the semiconductor device of this invention, these test steps are mounted as a built-in self test (BIST) circuit. Since the number of test steps for the above method is minimized, the required number of circuits and the circuit size can be reduced for a circuit wherein these steps are mounted. Accordingly, a reduction in power consumption can also be realized.
REFERENCES:
patent: 4812982 (1989-03-01), PeBenhofer
patent: 5107501 (1992-04-01), Zorian
patent: 5294911 (1994-03-01), Uchida et al.
patent: 5946246 (1999-08-01), Jun et a
Miyatake Hisatada
Mori Yotaro
Tanaka Masahiro
Baran Mary Catherine
Canale Anthony J.
Hoff Marc S.
Walsh Robert A.
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