Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-01-09
2002-12-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, 37, 37, 37
Reexamination Certificate
active
06496433
ABSTRACT:
BACKGROUND OF THE INVENTION
This application claims the benefit of a Japanese Patent Application No.2000-054878 filed Feb. 29, 2000, in the Japanese Patent Office, the disclosure of which is hereby incorporated by reference.
1. Field of the Invention
The present invention generally relates to semiconductor devices and semiconductor device testing methods, and more particularly to a semiconductor device having a test mode, and to a semiconductor device testing method for testing such a semiconductor device.
Generally, when guaranteeing functions and performances of semiconductor devices such as semiconductor memory devices at the time of forwarding the semiconductor devices or, when a user checks abnormalities of the semiconductor device, a command is input to the semiconductor device to switch an operation mode thereof to a test mode, so as to carry out various kinds of tests. The switching of the operation mode of the semiconductor device from a normal mode to the test mode is often referred to as a test mode entry.
2. Description of the Related Art
In a conventional synchronous dynamic random access memory (SDRAM), the test mode entry is made by inputting a command to the SDRAM in synchronism with an external clock, for example. In addition, in a case where the command is determined by a predetermined combination of signals such as a chip select signal and an address strobe signal, the test mode entry is erroneously made if the predetermined combination of the signals occurs accidentally. Accordingly, it is possible to use a command signal exclusively for switching the operation mode of the semiconductor device to the test mode.
On the other hand, in an asynchronous DRAM, it is not possible to employ a test mode entry system of the type employed in the SDRAM, because the asynchronous DRAM does not use an external clock. Thus, in one example of the conventional asynchronous DRAM, the test mode entry is made by applying a super-high voltage which is higher than a voltage which is normally applied with respect to the asynchronous DRAM.
In addition, the DRAM is supplied with a core power supply voltage and an output power supply voltage. The core power supply voltage is used in a core section of the DRAM, such as peripheral circuits and a memory cell array within the DRAM. The output power supply voltage is used in an output section of the DRAM, such as an output circuit within the DRAM. Normally, mutually different voltages are used for the core power supply voltage and the output power supply circuit, and for this reason, the core power supply voltage and the output power supply voltage are supplied to the DRAM via mutually different power supply pads. However, regardless of whether the DRAM is the synchronous or the asynchronous type, there are demands to reduce the number of pads in order to improve the integration density of the DRAM. Hence, with regard to the power supply pads, it is conceivable to use the same voltage for the core power supply voltage and the output power supply voltage, so that the core power supply voltage and the output power supply voltage can be supplied to the DRAM via common power supply pads.
However, if the conventional DRAM were constructed to use the common power supply pads for supplying the core power supply voltage and the output power supply voltage to the DRAM, and the core power supply voltage is supplied to the DRAM in the test mode in order to measure an active current in the core section, for example, this core power supply voltage would also be supplied to the output section of the DRAM. Consequently, it would become impossible to separate the active current and an output current from the output circuit within the DRAM, for example, thereby making it impossible to carry out the originally intended test during the test mode.
Therefore, in the conventional semiconductor devices, if an attempt is made to supply the same power supply voltage via the common power supply pads to the circuits which are mutually connected but are originally supplied with mutually different power supply voltages, there was a problem in that it is impossible to carry out the originally intended test with respect to the semiconductor device during the test mode.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and semiconductor device testing method, in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device and a semiconductor device testing method, which enable the originally intended test to be carried out with respect to the semiconductor device during the test mode, even when the same power supply voltage is supplied via the common power supply pads to circuits which are mutually connected but are originally supplied with mutually different power supply voltages.
Still another object of the present invention is to provide a semiconductor device having a normal mode and a test mode for testing the semiconductor device, comprising a first circuit which receives an input signal, a test signal and an output enable signal, and outputs the input signal in response to the output enable signal, a second circuit which is coupled to the first circuit and outputs the input signal obtained from the first circuit, and power supply pads which receive a power supply voltage which is supplied in common to the first circuit and the second circuit, where the first circuit fixes an output impedance of the second circuit to a high-impedance regardless of the output enable signal when the test signal indicates the test mode. According to the semiconductor device of the present invention, it is possible to carry out the originally intended test with respect to the semiconductor device during the test mode, even when the same power supply voltage is supplied via the common power supply pads to circuits which are mutually connected but are originally supplied with mutually different power supply voltages.
The semiconductor device may further comprise a memory section which outputs the input signal to the first circuit. In addition, the semiconductor device may further comprise a logic circuit which generates the output enable signal based on a command signal, and a test mode judging circuit which generates the test signal based on the command signal and an address signal.
A further object of the present invention is to provide a semiconductor device testing method for testing a semiconductor device in a test mode, where the semiconductor device also has a normal mode and is constructed to supply a common power supply voltage to first and second circuits thereof which are mutually coupled, and the semiconductor device testing method comprises the steps of (a) controlling the first circuit to output an input signal to the second circuit in response to an output enable signal when a test signal indicates the normal mode, and (b) measuring a current at an arbitrary node within the first circuit in a state where an output impedance of the second circuit is fixed to a high-impedance, regardless of the output enable signal, when the test signal indicates the test mode. According to the semiconductor device testing method of the present invention, it is possible to carry out the originally intended test with respect to the semiconductor device during the test mode, even when the same power supply voltage is supplied via the common power supply pads to circuits which are mutually connected but are originally supplied with mutually different power supply voltages.
The semiconductor device testing method may further comprise the step of (c) outputting the input signal from a memory section to the first circuit. In addition, the semiconductor device testing method may further comprise the steps of (d) generating the output enable signal based on a command signal, and (e) generating the test signal based on the command signal and an address signal.
Other objects and further features of the present invention will be ap
Funyu Akihiro
Okumura Yasuhiro
Takahashi Yoshitaka
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Nelms David
Yoha Connie C.
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