Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2006-05-30
2010-06-15
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S718000
Reexamination Certificate
active
07739559
ABSTRACT:
A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.
REFERENCES:
patent: 5303198 (1994-04-01), Adachi et al.
patent: 5343429 (1994-08-01), Nakayama et al.
patent: 5493531 (1996-02-01), Pascucci et al.
patent: 5671229 (1997-09-01), Harari et al.
patent: 5680363 (1997-10-01), Dosaka et al.
patent: 5715423 (1998-02-01), Levy
patent: 5802551 (1998-09-01), Komatsu et al.
patent: 5996041 (1999-11-01), Kim
patent: 6040997 (2000-03-01), Estakhri
patent: RE36732 (2000-06-01), Miyamoto
patent: 6643196 (2003-11-01), Sugio
patent: 6834323 (2004-12-01), Dover et al.
patent: 6865133 (2005-03-01), Tsukidate et al.
patent: 6937533 (2005-08-01), Hojo et al.
patent: 7085167 (2006-08-01), Lee et al.
patent: 0477503 (1992-04-01), None
patent: 2066797 (1990-03-01), None
patent: 04137077 (1992-05-01), None
patent: 5150913 (1993-06-01), None
patent: 07105691 (1995-04-01), None
patent: 8007597 (1996-01-01), None
patent: 2004079602 (2004-03-01), None
patent: 2004342187 (2004-12-01), None
Arimoto, K., at al., A Circuit Design of Intelligent CDRAM with Automatic Write Back Capability. IEEE 1990 Symposium on VLSI Circuits, pp. 79-80, 1990.
Dosaka, Katsumi et al., A 100MHz 4Mb Cache DRAM with Fast Copy-Back Scheme, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 148-149, 1992.
Kawamoto Satoru
Niimi Makoto
Suzuki Norikatsu
Chung Phung M
Spansion LLC
LandOfFree
Semiconductor device and program data redundancy method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and program data redundancy method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and program data redundancy method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4163751