Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-18
2002-12-17
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S296000
Reexamination Certificate
active
06495874
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process for production thereof. More particularly, the present invention is intended to provide a semiconductor device containing a precision capacitive element and a process for production thereof.
2. Description of the Related Arts
Electronic machines and equipment are becoming smaller in size and lighter in weight, and are improving in performance and expanding in functions. This movement is accelerating the trend toward integrating linear or analog circuits (essential for AV machines and communication instruments) with digital circuits into a single semiconductor device (LSI). These circuits need precision capacitive elements, which are conventionally of DFC (Double Poly Capacitor) type or MIM (Metal-Insulator-Metal) type. The former type is composed of two polysilicon layers and one capacitive insulating film held between them. The latter type is composed of two metal layers and one capacitive insulating film held between them.
A capacitive element of DPC type is disclosed in Japanese Patent Laid-open No. HEI 9(1997)-36313. It has capacitive electrodes constructed of polysilicon layers which are semiconductor layers. Therefore, a small depletion layer occurs in the capacitive electrode itself no matter how large the amount of impurities added to polysilicon may be. The depletion layer thus formed fluctuates in width depending on the potential applied across the capacitive electrodes. This leads to fluctuation in capacitive value. Therefore, the capacitive element of DPC type does not suit circuits which need a very high precision.
In contrast, the capacitive element of MIM type, in which the capacitive electrodes are made of metal, does not permit a depletion layer to occur. Therefore, it offers the advantage of keeping a constant capacitive value regardless of potential across the electrodes. For this reason, it is common practice to use capacitive elements of MIM type for precision analog circuits.
A capacitive element of MIM type and a process for production thereof are disclosed in, for example, Japanese Patent Laid-open No. HEI 8(1996)-181282.
The process is illustrated in FIGS.
3
(
a
) to
3
(
d
).
On a semiconductor substrate
41
is deposited a silicon oxide film
42
. On the silicon oxide film
42
is deposited a first metal layer
43
. From this metal layer
43
are formed a lower electrode
43
a and a wiring
43
b by patterning through a mask of resist pattern (not shown) formed by photolithography. See FIG.
3
(
a
).
On the semiconductor substrate
41
is deposited an oxide film
44
by a plasma CVD method. On the oxide film
44
is formed an SOG (Spin On Glass) film
45
by spin coating. The SOG film
45
undergoes etch-back by RIE (reactive ion etching) to such an extent that the underlying oxide film
44
is exposed. As a result, the SOG film
45
partly remains on the vertical step of the first metal layer
43
, thereby moderating the slope angle of the step. Furthermore, an oxide film
46
is formed on the semiconductor substrate
41
by a plasma CVD method. See FIG.
3
(
b
).
A resist pattern (not shown) having an opening above the lower electrode
43
a
is formed by photolithography. Using this resist pattern as a mask, etching by RIE is performed on the oxide film
44
and
46
so as to form an opening
47
through which the surface of the lower electrode
43
a
is exposed. On the semiconductor substrate
41
is deposited a plasma nitride film
48
which functions as the capacitive insulating film. See FIG.
3
(
c
).
A resist pattern (not shown) having an opening above the wiring
43
b
is formed by photolithography. Using this resist pattern as a mask, etching by RIE is performed on the oxide film
44
and
46
and the plasma nitride film so as to form an opening
49
through which the surface of the wiring
43
b
is exposed. See FIG.
3
(
d
).
On the semiconductor substrate
41
is further deposited a second metal layer, which is subsequently undergoes patterning using a resist pattern (not shown) as a mask formed by photolithography, so that an upper electrode
50
a
is formed above the lower electrode
43
a
and a wiring
50
b
is formed above the wiring
43
b
. In this way there are obtained a capacitive element
52
of MIM structure and a wiring
51
of laminate structure, the former being composed of the lower electrode
43
a
, the capacitive insulating film
46
and the upper electrode
50
a,
and the latter being composed of the wiring
43
b
and the wiring
50
b.
See FIG.
3
(
d
).
In addition, Japanese Patent Laid-open No. HEI 9(1997)-92786 discloses a capacitive element of MIM type and a process for production thereof, as explained in the following.
The process is illustrated in FIGS.
4
(
a
) to
4
(
f
).
On a semiconductor substrate
60
is deposited a first metal layer
61
, which is subsequently patterned as desired. Then, on the semiconductor substrate
60
is deposited an insulating layer
62
, the surface of which is subsequently planarized by CMP (Chemical Mechanical Polish) method or the like. See FIG.
4
(
a
).
The insulating layer
62
is etched using a resist pattern (not shown) as a mask formed by photolithography to such an extent that the first metal layer
51
is exposed, so that openings
63
a
and
63
b
are formed. See FIG.
4
(
b
).
On the semiconductor substrate
60
is entirely deposited a thin dielectric film
64
, which functions as a capacitive insulating film afterward. On the thin dielectric film
64
is deposited by photolithography a resist pattern
65
which has an opening above the opening
63
b.
This opening functions as a connection for the metal wiring layer. See FIG.
4
(
c
).
The dielectric film
64
undergoes etching through the resist pattern
65
as a mask, so that the first metal layer
61
is exposed at the bottom of the opening
63
b
. See FIG.
4
(
d
).
On the entire surface of the semiconductor substrate
60
is deposited a second metal layer
65
. See FIG.
4
(
e
).
The second metal layer
65
is patterned into a desired form through a resist pattern (not shown) as a mask formed by photolithography, so as to form an upper electrode
65
a
and a wiring
65
b.
In this way there is formed a capacitive element
66
of MIM structure composed of the lower electrode
61
, the dielectric film
64
and the upper electrode
65
a,
and also there is formed the wiring
65
b
connected to the lower electrode
61
. See FIG.
4
(
f
).
The conventional capacitive elements of MIM structure as mentioned above, however, have posed the following problems as recent semiconductor devices are required to have finer fabrication and faster operating speeds. That is, as semiconductor devices have came to have finer fabrication and faster operating speeds, the metal wiring has become multi
4
ayered. And in the circuits containing analog elements such as capacitive elements, three to six layers of wiring is now required.
The process of forming multi-layered wiring requires that each layer is planarized sufficiently. The result of failure in planarization is that the subsequent step to finely pattern the metal layer or to form a small opening in the interlayer film has to be carried out on an uneven surface. Photolithography on an uneven surface suffers a decrease in focusing margin, which makes it difficult to form fine and precision patterns and openings. Making each layer flat is a key factor in the process of forming multilayered wiring. One way to meet this requirement is to planarize the insulating film between metal wiring layers by CMP method.
The disadvantage of the above-mentioned conventional process for producing capacitive elements is that the opening
47
or
63
a
(for a capacitive element to be formed therein) causes the surface of the upper electrode
50
a
or
65
a
to have unevenness which is originated in the steps of the underlying interlayer insulating film. Such steps present difficulties in the fine patterning of the upper electrode
50
a
or
65
a
and also in the pattering of mult
Kawamura Akio
Tsuchida Takahiro
Meier Stephen D.
Sharp Kabushiki Kaisha
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