Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-03-02
2003-04-29
Picardat, Kevin M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000
Reexamination Certificate
active
06555925
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-055703, filed Mar. 3, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a producing method thereof, and particularly to the technique of dicing.
A plurality of semiconductor integrated circuits are generally produced on a single semiconductor wafer. Normally, elements and wiring are formed on a wafer, the wafer is cut along dicing lines, and the individual integrated circuit is divided into a plurality of chips.
Alignment marks for alignment of each layer are formed in a dicing line area. Therefore, the alignment marks may be damaged by the dicing and a material used for the alignment marks may adhere to the chips. Generally, the same material as that of the wiring is used for the alignment marks. In a conventional semiconductor integrated circuit, aluminum (Al) is used as the wiring material and a serious problem does not particularly occur even if Al adheres to the chips.
Recently, a request to use copper (Cu) for the wiring as the wiring material of a lower resistance has been increased. It is known that Cu gives a bad influence to the element characteristics such as the variation in the threshold voltage of the semiconductor element since Cu easily diffuses in SiO
2
and Si. In the producing process of the semiconductor element, the diffusion of Cu to peripheral elements can be prevented by covering the Cu wiring with a diffusion prevention film.
At the time of dicing, however, the alignment marks formed in the dicing line area are damaged, and flying Cu adheres to the side surface or the back surface of the chip. Cu adhering to the chip diffuses to the element area by a following thermal process and gives a bad influence to the element characteristics.
BRIEF SUMMARY OF THE INVENTION
The present invention is achieved to solve the above-described problem of the prior art, and its object is to provide a semiconductor device using the Cu wiring which can solve the problems caused by the dicing and also provide a producing method of the semiconductor device.
A first invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a litho-graphic process is formed of a wiring material which is copper or includes copper as a main component, and the method comprises forming the alignment mark entirely in an area outside an area where dicing is to be executed.
In the first invention, it is preferable that the alignment mark is entirely formed in an area where wirings and elements are to be formed.
According to this invention, the alignment mark is entirely formed in an area outside an area (a first area) where the dicing is to be executed and, therefore, the alignment mark is not damaged in the dicing process. For this reason, as copper constituting the alignment mark does not adhere to the chips at the time of the dicing, it is possible to solve the problem that the copper adhering to the semiconductor chips diffuses to the element area by the thermal treatment and thereby give a bad influence to the element characteristics and the like as seen in the prior art.
In addition, by forming the alignment mark entirely in an area (i.e. a second area) where the wirings and elements are to be formed, an interval between the first area and the second area can be made small. (When the first area and the second area have same width, the interval therebetween becomes zero.) Therefore, an area other than the second area can be made smaller.
A second invention is a semiconductor device in which at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component, and the alignment mark is entirely formed inside a semiconductor chip separated by a dicing process.
In this invention, as the alignment mark is entirely formed inside the semiconductor chip, the alignment mark is not damaged at the time of dicing. Therefore, copper constituting the alignment mark does not adhere to the semiconductor chip and it is thereby possible to solve the problem that the element characteristics and the like are worsened by diffusion of copper.
A third invention is a method of producing a semiconductor device in which at least one pattern region corresponding to at least one alignment mark to be used in an exposure process of a lithographic process is formed of a wiring material which is copper or includes copper as a main component. After forming the pattern region corresponding to the alignment mark, the wiring material of the pattern region is removed or inactivated.
According to this invention, as the wiring material of the pattern region corresponding to the alignment mark is removed or inactivated, copper that is the wiring material does not adhere to the semiconductor chips even if the alignment mark is damaged at the time of dicing. Therefore, it is possible to solve the problem that the copper adhering to the semiconductor chips diffuses to the element area by the thermal treatment and thereby give a bad influence to the element characteristics and the like as seen in the prior art.
After the process of removing or inactivating the wiring material has been executed, the pattern where the wiring material has been removed or inactivated functions as the alignment mark.
A fourth invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a litho-graphic process is formed of a wiring material which is copper or includes copper as a main component. In this method, the wiring material which is separated from a region where the alignment mark is formed and which adheres to a semiconductor chip, in a dicing process, is removed or inactivated.
According to this invention, the wiring material adhering to the semiconductor chips in the dicing process is removed or inactivated after the dicing process. Therefore, it is possible to solve the problem that the copper adhering to the semiconductor chips diffuses to the element area by the thermal treatment and thereby give a bad influence to the element characteristics and the like as seen in the prior art.
A fifth invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a litho-graphic process is formed of a wiring material which is copper or includes copper as a main component. This method comprises a step of covering a pad formed by using the wiring material, with a protection film, before a dicing process, a step of removing or inactivating the wiring material which is separated from a region where the alignment mark is formed and which adheres to a semiconductor chip, in the dicing process, and a step of removing a part of the protection film to expose a surface of the pad after removing or inactivating the wiring material.
According to this invention, the wiring material adhering to the semiconductor chips in the dicing process is removed or inactivated. Therefore, it is possible to solve the problem that the copper adhering to the semiconductor chips diffuses to the element area by the thermal treatment and thereby give a bad influence to the element characteristics and the like as seen in the prior art.
Further, as the pad area is covered at the time of removing or inactivating the wiring material adhering to the semiconductor chips, it is possible to prevent the wiring material in the pad area from being removed or inactivated.
A sixth invention is a method of producing a semiconductor device in which at least one alignment mark to be used in an exposure process of a litho-graphic process is formed of a wiring material which is copper or includes copper as a main component. Grooves for dividing a semiconductor wafer into semiconductor chips are formed on a surface of the semiconductor
Higashi Kazuyuki
Kajita Akihiro
Kaneko Hisashi
Matsunaga Noriaki
Shibata Hideki
Kabushiki Kaisha Toshiba
Picardat Kevin M.
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