Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-02
2002-12-10
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S413000, C257S384000
Reexamination Certificate
active
06492696
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-133752 filed on May 2, 2000, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a process of manufacturing the same. In particular it relates to a semiconductor device of an LDD structure comprising a MOS transistor in which a silicide film is provided at least on a surface of a source/drain region, and a process of manufacturing the same.
2. Description of Related Art
As integration of semiconductor integrated circuits progresses, MOS transistors comprising the circuits are required to be further miniaturized. For example, gate length typically in the order of submicron or half micron tends to become as small as 0.35 &mgr;m, 0.25 &mgr;m or 0.18 &mgr;m.
Smaller gate length is advantageous in high-speed operation. However, it causes short channel effect, reduction of threshold voltage (Vth) and decrease in dielectric strength at a source/drain region. Further, favorable contact holes of minuscule area and low resistance are required.
To inhibit the short channel effect, commonly known is a technique for forming a shallow source/drain region and utilizing an LDD (Lightly Doped Drain) structure. Further, also known is a method of forming a silicide film on the surfaces of a source/drain region and a gate electrode to reduce contact resistance.
However, according to the miniaturization of the gate length, the source/drain region tends to be shallower. For example, in the case where the gate length is 0.50 to 0.35 &mgr;m, the depth of the source/drain region is 200 to 150 nm, and in the case where it is 0.25 &mgr;m, the depth of the source/drain region is as extremely small as about 80 nm. Accordingly, where the silicide film is formed on such a shallow source/drain region, it is required to reduce an amount of the silicon substrate to be consumed by the formation of the silicide film. If the silicon substrate is consumed in a large amount, the silicide film will penetrate the source/drain region to reach a PN junction and break the PN junction.
For example, it has been reported that, when a cobalt silicide film is formed on the surface of the source/drain region of a transistor, a spike of about 100 nm in length is generated so as to extend along the source/drain region. Thereby leak current at the PN junction of the source/drain region is increased (cf. Conference of the Japan Society of Applied Physics, 1996 Autumn, Summary II, p589).
Accordingly, as shown in
FIG. 2
, a monocrystalline or polycrystalline silicon layer is selectively and epitaxially grown on a source/drain region
21
. Then a titanium film is formed thereon and thermally treated to form a titanium silicide film
23
on the surface of the monocrystalline or polycrystalline silicon layer
22
(cf. Japanese Unexamined Patent Publication No. Hei 10 (1998)-92949). According to this method, silicon can be supplied by the monocrystalline or polycrystalline silicon layer
22
even if the silicon is largely consumed at the formation of the titanium silicide film
23
, so that the titanium silicide film
23
is prevented from penetrating the source/drain region
21
.
However, by the selective epitaxial growth of the monocrystalline or polycrystalline silicon layer
22
on the source/drain region
21
, the monocrystalline or polycrystalline silicon layer
22
is also deposited on sidewall spacers
25
of a gate electrode
24
. Therefore the titanium silicide film
23
is also formed on the sidewall spacers
25
, which causes short circuit between the source/drain region
21
and the gate electrode
24
.
Further, as shown in
FIG. 3
, there has been proposed a method of forming a source/drain region
33
of sufficient thickness by providing a gate electrode
31
in a recess of a silicon substrate
32
(e.g., see Japanese Unexamined Patent Publication No. Hei 11 (1999)-154749). According to this method, the source/drain region
33
is formed with a sufficient thickness so that penetration of a silicide film
34
through the source/drain region
33
is prevented.
However, in comparison with a MOS transistor formed on a flat silicon substrate, the thus formed transistor increases parasitic capacitance between the gate electrode
31
and the source/drain region
32
, which harmfully influences on high-speed operation.
Still further, as shown in FIGS.
4
(
a
) to
4
(
e
), a method has been proposed by, e.g., Japanese Unexamined Patent Publication No. Hei 11 (1999)-40817 in which a LOCOS film
42
is formed on a surface silicon layer
41
of an SOI substrate (FIG.
4
(
a
)), the LOCOS film
42
is etched away (FIG.
4
(
b
)) to thin a channel region
43
(a recessed channel region; FIG.
4
(
c
)), and then a metal film
45
is formed on the entire surface of the substrate (FIG.
4
(
d
)) to form a silicide film
46
(FIG.
4
(
e
)). Since this method utilizes the SOI substrate, the depth of a source/drain region
44
can be controlled by adjusting the thickness of the surface silicon layer
41
. Accordingly the source/drain region
44
of relatively large depth can be formed by a common step for forming the source/drain region.
However, when this method is applied to a bulk substrate, diffusion of impurities in the source/drain region due to thermal treatment must be strictly controlled in order to adjust the depth of the source/drain region. Further, an additional step of forming the sidewall spacers on the gate electrode is required for the formation of an LDD region to prevent short channel effect and for the formation of the silicide film to prevent short circuit between the gate electrode and the source/drain region. Moreover, since a common step of forming the LDD region requires a thermal treatment for forming the source/drain region and another thermal treatment for forming the silicide film after ion implantation for forming the LDD region, the resulting LDD region is diffused too much in the lateral direction, which leads to insufficient prevention of the short channel effect.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the above-described problems. An object of the present invention is to provide a highly reliable semiconductor device in which short channel effect and short circuit are effectively inhibited by a relatively easy technique even if the semiconductor device includes an LDD region and a silicide film in the source/drain region, and a process of manufacturing the same.
According to the present invention, provided is a semiconductor device comprising: a gate electrode formed on a semiconductor substrate through the intervention of a gate insulating film; and a source/drain region provided with a silicide film on its surface and formed in the semiconductor substrate, wherein the source/drain region has an LDD region whose surface is partially or entirely tapered and an interface between the semiconductor substrate and the silicide film in the source/drain region is located higher than a surface of the semiconductor substrate below the gate electrode.
Further, according to the present invention, provided is a process of manufacturing a semiconductor device comprising the steps of: forming a LOCOS oxide film on a semiconductor substrate; partially removing the LOCOS oxide film to form a recess on the semiconductor substrate; burying a gate electrode in the recess through the intervention of a gate insulating film; performing ion implantation using the gate electrode and the remaining LOCOS oxide film as a mask to form a source/drain region; forming a silicide film at least on a surface of the source/drain region; and forming an LDD region in the semiconductor device below both sides of the gate electrode.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and sp
Adan Alberto O.
Morimoto Hidenori
Lindsay Jr. Walter L.
Niebling John F.
Nixon & Vanderhye P.C.
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