Semiconductor device and process for producing the same

Details Semiconductor device and process for producing the same Semiconductor device and process for producing the same

2000-12-22

2002-09-10

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S403000

Reexamination Certificate

active

06448620

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device for use as a switching element.
BACKGROUND OF THE INVENTION
Recently, the needs of semiconductor switches such as analog switches, semiconductor relays and the like are increasing for use as switches for turning high frequency signals on or off. To use these semiconductor switches for turning on or off high frequency signals, they are required to have linear current-voltage characteristics (having no offset voltage) and low on-state resistance and also to have a small output capacitance in the signal-OFF state so as to improve the high frequency cut-off characteristics.
SOI (silicon-on-insulator)-LDMOSFET (lateral double-diffused MOSFET) is known as a semiconductor element capable of meeting these requirements.
A conventional SOI-LDMOSFET is constructed as follows, using a SOI substrate which comprises a semiconductor substrate (
1
) formed from a single crystal silicon, an insulating layer (
2
) formed from a silicon oxide on the semiconductor substrate (
1
), and a semiconductor layer (
3
) formed from a single crystal silicon on the insulating layer (
2
) (see FIG.
10
A)).
As shown in
FIG. 10A
, in this SOI-LDMOSFET, a p
+
-type well region (
5
) and an n
++
-type drain region (
4
) are formed with a space therebetween in the n-type semiconductor layer (
3
), and an n
++
-type source region (
6
) is further formed in the p
+
-type well region (
5
). In this regard, a part of the p
+
-type well region (
5
) and the n-type semiconductor layer (
3
) are located between the n
++
-type source region (
6
) and the n
++
-type drain region (
4
).
In addition, a gate electrode (
9
) is formed from, for example, a poly-silicon, which is disposed on a gate-insulating layer (
8
) formed on the p
+
-type well region (
5
) between the n
++
-type source region (
6
) and the n
++
-type drain region (
4
). The gate electrode (
9
) is formed overhanging the n
++
-type source region (
6
) and the drift region located between the p
+
-type well region (
5
) and the n
++
-type drain region (
4
) in the n-type semiconductor layer (
3
), respectively, taken into account margins for a shift of the position in the process of production.
A source electrode (
11
) and a drain electrode (
10
) are formed on the n
++
-type source region (
6
) and the n
++
-type drain region (
4
), respectively.
In the conventional SOI-LDMOSFET constructed above as shown in
FIG. 10A
, while a voltage is being applied across the n
++
-type source region (
6
) and the n
++
-type drain region (
4
) through the source electrode (
11
) and the drain electrode (
10
), not less than a predetermined voltage is being applied to the gate electrode (
9
), so that a channel is formed, under strong inversion condition, in a part of the p
+
-type well region (
5
) under the gate electrode (
9
), and that current flows between the n
++
-type source region (
6
) and the n
++
-type drain region (
4
) through the channel (the state of ON).
When the voltage to the gate electrode is decreased, the p
+
-type well region (
5
) turns into the original p-type Layer, so that a PN junction in reverse bias is formed between the p
+
-type well region and the n
++
-type drain region (
4
). As a result, current does not flow between the n
++
-type source region (
6
) and the n
++
-type drain region (
4
).
In the SOI-LDMOSFET shown in
FIG. 10A
, a part of the n-type semiconductor layer (
3
) between the p
+
-type well region (
5
) forming the channel and the n
++
-type drain region (
4
) is called a drift region (
20
), and the impurity concentration NO of the drift region (
20
) is so selected as to satisfy the RESURF condition expressed by the following equation (1).
Tsoi×NO≈
1×10
12
(atm/cm
2
)  (1)
wherein Tsoi represents the thickness of the drift region.
As described above, the conventional SOI-LDMOSFET achieves high withstand voltage by selecting the impurity concentration NO of the drift region (
20
) so that the above RESURF condition for providing optimal conditions relative to a surface electric field can be satisfied. In this regard, in the SOI-LDMOSFET shown in
FIG. 10A
, the impurity concentration NO of the drift region (
20
) is so selected as to be uniform over a whole of the drift region (
20
).
Lately, structures for further improving the withstand voltage of the SOI-LDMOSFET shown in
FIG. 10A
are proposed in U.S. Pat. Nos. 5,300,448, 5,412,241 and so on.
In the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448, the n-type drift region (
50
) locates between the drain region (
52
) having the drain electrode (
56
) formed thereon and the source region (
51
) having the source electrode (
54
) formed thereon as shown in
FIG. 11
, and the drift region (
50
) is so formed that the impurity concentration of the drift region (
50
) can linearly decrease as the distance from the drain region (
52
) increases. In addition, a space between the source region (
51
) and the drift region (
50
) has a gate electrode (
59
) formed therein spaced by the gate oxide layer (
58
) and a p-type base region (
60
) for forming a channel. Constructed as above, the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 succeeds in uniforming the surface and the internal electric field of the drift region (
50
) and thus further improving the withstand voltage.
However, the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 has a problem in that it is impossible to decrease the length of the drift region (
50
) (the length along which current flows). This disadvantage comes from the following structure: as shown in
FIG. 12
, the drift region is formed on the semiconductor layer (
3
) through a mask having a plurality of openings (
40
) which are formed so that the distance between each of the openings changes in order and such a semiconductor layer (
3
) is doped with a predetermined amount of impurity and then treated by heating, so that the impurity concentration of the drift region (
50
) changes in order. This structure makes it hard to shorten the length of the drift region (
50
). It is described in U.S. Pat. No. 5,300,448 that the length of the drift region (
50
) is 40 to 50 &mgr;m
Therefore, on-state resistance becomes higher because the length of the drift region (
50
) is long in the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448.
The SOI-LDMOSFET proposed in U.S. Pat. No. 5,300,448 has a further problem in that it is inevitably needed to decrease the thickness of the drift region (
50
) in order to improve the withstand voltage, which leads to poor heat release. This results in a problem that allowable current in the state of ON can not be increased.
The SOI-LDMOSFET proposed in U.S. Pat. No. 5,412,241 or the like provides the structure which makes it possible to decrease the on-state resistance and to improve the withstand voltage characteristics. However, this SOI-LDMOSFET has a gate-field plate structure and therefore has a problem in that the output capacitance is large.
In the meantime, the switch for turning a high frequency signal on or off is keenly demanded in the voltage class from 20 to 300 V. In case where a SOI-LDMOS of this class is constructed so as to have an ideal structural parameter, it is estimated that the optimal value of the length of the drift region is 1 to 15 &mgr;m. However, it is hard to form a drift region having an optimal length of 1 to 15 &mgr;m, because the method of producing the SOI-LDMOSFET disclosed in U.S. Pat. No. 5,300,448 has a problem in the processing precision.
The present invention is made to overcome the foregoing problems, and the first object of the present invention is to provide a semiconductor device capable of increasing allowable current in the state of ON while ensuring the demanded withstand voltage and decreasing output capacitance and on-state resistance.
T

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