Semiconductor device and process for manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257334, 257153, 438700, 438734, H01L 29744, H01L 2978

Patent

active

060752696

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a lateral type semiconductor device such as power MOSFET, IGBT, GTO, SIT and SI thyristor, wherein a gate structure is formed in a depressed portion having a particularly large aspect ratio (length/width ratio), that is the depressed portion has a larger depth than a width, and a method of manufacturing such a lateral type semiconductor device.


TECHNICAL BACKGROUND

The power semiconductor device of the kind mentioned above has been widely used as a power supply device, and has been described in the following literatures. a triode", Nikkei Electronics, 50.about.61, Sep. 27, 1971 versus Analog Transistor (Static Induction Transistor)", IEEE Trans. on Electron Device, ED-22(4), 185 (1975) "Denshi-Tsushin Institute Technical Research Report", ED81-84 (1981) Electron Device, ED-31, 157 (1984) On-resistance", IEDM Tech. Dig., 736 (1985) Light-Trigger Thyristor with Over Voltage Self Protection"
The miniaturization of a semiconductor device has been effected in accordance with a progress in the high performance and low consumption of electric power, and thus the formation of a recessed portion having a high aspect ratio has been required. For instance, in order to form field-limiting rings, element separation regions and via holes in an insulated layer, and to manufacture power semiconductor devices having a notched gate structure such as a static induction (SI) thyristor, it is necessary to form a trench structure having a high aspect ratio.
The selective etching has been generally used to form the trench structure. The etching is roughly classified into isotropic etching and anisotropic etching. The isotropic etching includes wet-etching and dry-etching, and the wet-etching has an advantage, in general, that the etching speed is higher than that of the dry etching. A solution of hydrogen fluoride and nitric acid is generally used as an etching solution for the isotropic wet-etching of a silicon substrate, while a mask made of silicon oxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4), and silicon oxynitride (SiNO) is used.
The isotropic etching can be mainly obtained in thermally non-equilibrium of a plasma excited gas. In this case, it is known that a trench structure of a higher aspect ratio can be obtained by optimizing gas composition, gas pressure, and substrate temperature.
The above isotopic etching has a high etching speed but has s demerit that the aspect ratio could not be made high, because in case of effecting deep etching, an etching in a lateral direction is carried out underneath the mask to a substantially same extent as the etching in the depth direction.
Thus, in the past, the isotropic etching has been widely used to form the trench structure having a high aspect ratio. However it is actually impossible to form the trench structure having a depth of more than ten .mu.ms, because the isotropic etching has a low etching speed. By conducting the isotropic etching for a long time, it is theoretically possible to obtain a deep recess, but it is actually difficult to perform the etching process for a long time because the consumption of the mask is increased during a long etching so that the structure of a desired profile could not be obtained and a throughput becomes low.
The above problem will be described in more detail with reference to an example in which an SI thyristor is manufactured as one of the power semiconductor devices with the notched gate structure. FIG. 1 shows a conventional notched gate structure formed by the isotropic etching. On one surface of an N-type silicon substrate 1 there is formed a p-type anode region 2 by diffusing p-type impurities, and an anode electrode 3 is formed on the anode region. On the other surface of the silicon substrate 1 there is formed a cathode region 4 by diffusing a large amount of n-type impurities, and a cathode electrode 5 is formed on the cathode region. A recess 6 having a width W.sub.G is forme

REFERENCES:
patent: 4403396 (1983-09-01), Stein
patent: 4774555 (1988-09-01), Kohn et al.
Patent Abstracts of Japan, vol. 017, No. 466 (E-1421) Aug. 25, 1993, JP 5-110105.
Patent Abstracts of Japan, vol. 010, No. 332 (E-453) Nov. 12, 1986, JP 61-137371.
Patent Abstracts of Japan, vol. 017, No. 672 (E-1474) Dec. 10, 1993, JP 5-226273.
Patent Abstracts of Japan, vol. 096, No. 001, Jan. 31, 1996, JP 7-235662.
Patent Abstracts of Japan, vol. 017, No. 264 (E-1370) May 24, 1993, JP 5-007002.

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