Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-04-26
2003-09-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C451S041000, C438S692000
Reexamination Certificate
active
06613688
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor devices, and more particularly, to a semiconductor device and a process for generating an etch pattern on a semiconductor device.
RELATED ART
During the manufacture of a semiconductor device, it may be necessary to planarize the surface of a semiconductor device as one or more of the manufacturing steps. Chemical Mechanical Polishing is one such process used to planarize surfaces of semiconductor devices. However, it is difficult to guarantee uniformity of the planarization because of varying layouts on the semiconductor device. The nonuniformity in thickness, caused by interactions between the layout and the polishing process, can result in electrical opens, high resistance contacts, electrical shorts, or other leakage paths in the integrated circuits.
Traditionally, tiling has been used in forming semiconductor devices to help solve the varying height problem. Tiles are printed dummy features used to fill in the low areas. There are several ways of choosing where to place the dummy features. A rule based process for tiling, or placing the dummy features, typically includes creating a circuit layout, defining a buffer zone (typically in a range of approximately 0.5-10 microns) around active features within the layout, and combining the circuit layout with the buffer zone to determine excluded areas. All other areas are available for tiling. Rule based tiling places tiles regardless of circuit density. Model based tiling is used to choose locations to place the tiles by taking into account the circuit density and other topographical considerations. However, in some cases, the use of tiles, or dummy features cannot solve all of the layout topographical uniformity problems.
Therefore, a need exists for a way to provide for better topographical uniformity of the surface of a semiconductor device.
REFERENCES:
patent: 6040210 (2000-03-01), Burns et al.
patent: 6045435 (2000-04-01), Bajaj et al.
patent: 6077745 (2000-06-01), Burns et al.
patent: 6114725 (2000-09-01), Furukawa et al.
patent: 6174766 (2001-01-01), Hayashi et al.
patent: 6194038 (2001-02-01), Rossman
patent: 6362057 (2002-03-01), Taylor et al.
patent: 6362074 (2002-03-01), Bohr
patent: 6380084 (2002-04-01), Lim et al.
patent: 6396158 (2002-05-01), Travis et al.
patent: 6435942 (2002-08-01), Jin et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6452284 (2002-09-01), Sheck
patent: 6492227 (2002-12-01), Wang et al.
Lee et al, “Using Smart Dummy Fill and Selective Reverse Etchback for aPattern Density Equalization,” CMP-MIC Conference 2000 IMIC—500P/00/0255, pp. 255-257.
Brown Thomas M.
Haines Jeffrey C.
Travis Edward O.
Hill Damiel D.
Luk Olivia
Motorola Inc.
Niebling John F.
Vo Kim-Marie
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