Semiconductor device and methods for fabricating same

Details Semiconductor device and methods for fabricating same Semiconductor device and methods for fabricating same

2009-10-21

2011-12-13

Pizarro Crespo, Marcos D (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000, C257S036000, C257S040000

Reexamination Certificate

active

08076703

ABSTRACT:
A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

REFERENCES:
patent: 6392278 (2002-05-01), Kimura
patent: 7420202 (2008-09-01), Adams et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2007/0045747 (2007-03-01), Kohyama
Bo, Xiang-Zheng, et al. “Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors,” 2006 IEEE International SOI Conference Proceedings. pp. 19-20.

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