Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-02-01
2002-10-22
Jackson, Jr., Jerome (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S686000, C257S723000, C257S738000
Reexamination Certificate
active
06469370
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of production of the semiconductor device, and more particularly to a semiconductor device having a chip size package (CSP) structure and a method of production thereof.
In order to conform the shape and size of semiconductor devices to the chip shape and size as closely as possible, there has been proposed the CSP structure of semiconductor devices in which external output terminals are provided on the semiconductor device and enclosed in a resin material.
2. Description of the Related Art
A description will now be given of a conventional CSP semiconductor device with reference to
FIG. 11
, FIG.
12
and FIG.
13
.
FIG. 11
shows the conventional CSP semiconductor device
1100
.
FIG. 12
is a cross-sectional view of the conventional CSP semiconductor device
1100
taken along the one-dot chain line indicated in FIG.
11
.
FIG. 13
shows interconnections of the elements in the conventional CSP semiconductor device
1100
.
As shown in
FIG. 12
, in the conventional CSP semiconductor device
1100
, a semiconductor substrate
1101
, an internal wiring pattern
1102
, vias
1103
, a protective layer
1104
, an external wiring pattern
1105
, and projection electrodes
1106
are provided. The substrate
1101
contains an electronic circuit provided therein, and the electronic circuit includes terminals. The internal wiring pattern
1102
is provided in the substrate
1101
and connected to the electronic circuit terminals. The vias
1103
are made of aluminum (Al) and they are electrically conductive. The vias
1103
are connected to the internal wiring pattern
1102
. The vias
1103
are provided in the substrate
1101
and project from the protective layer
1104
. The protective layer
1104
is made of a resin material, such as polyimide, that is dielectric, and provided on the substrate
1101
. The external wiring pattern
1105
is made of copper (Cu) and connected to the vias
1103
which project from the protective layer
1104
. The projection electrodes
1106
are provided on the external wiring pattern
1105
.
In the above-described semiconductor device
1100
of
FIG. 13
, the protective layer
1104
is omitted for the sake of convenience and the interconnections of the elements
1103
,
1105
,
1106
and
1108
are shown.
At the final stage of the packaging, the semiconductor device
1100
is enclosed in an enclosure of a resin material, but only the upper edges of the projection electrodes
1106
are not covered with the enclosure. The enclosure of the conventional CSP chip is not illustrated in FIG.
12
.
In the above-described semiconductor device of
FIG. 13
, the positions of the projection electrodes
1106
on the chip are determined in a fixed manner by using the reflow of the solder of the external wiring pattern
1105
. The reflow of the solder of the external wiring pattern
1105
allows electrical connections between the pads
1108
and the projection electrodes
1106
. As the pitch of the projection electrodes
1106
can be larger than the pad pitch by the reflow of the solder of the external wiring pattern
1105
, it is possible to avoid the short-circuit of the projection electrodes
1106
when implementing the above-described semiconductor device on a main printed wiring board.
However, the pads
1108
are, as shown in
FIG. 13
, provided at peripheral portions on the chip surface. These pads are essentially the same as those used with existing wire bonding equipment. Each of the pads
1108
is, typically, in the size of 100 &mgr;m×100 &mgr;m, and the arrangement of the pads
1108
at the peripheral portions of the semiconductor chip will be detrimental to increasing the packaging density of the semiconductor device. The total number of transistors that can be mounted on the conventional CSP semiconductor device will be significantly restricted due to the size of the pads.
In the above-described semiconductor device
1100
, the external wiring pattern
1105
does not connect the pads
1108
and the projection electrodes
1106
by the shortest distance. Some of the external wiring pattern
1105
must be elongated to connect the peripheral pads
1108
and the projection electrodes
1106
, and this will degrade the electrical performance of the connections in the conventional CSP semiconductor device.
SUMMARY OF THE INVENTION
In order to overcome the problems described above, preferred embodiments of the present invention provide an improved semiconductor device that achieves a high packaging density of transistors on the semiconductor device as well as downsizing of the semiconductor device without degrading the electrical performance of the connections.
According to one preferred embodiment of the present invention, a semiconductor device includes: a semiconductor substrate; an electronic circuit which is provided in the substrate, the electronic circuit having terminals; an internal wiring pattern which is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals; a protective layer which is provided on the substrate, the protective layer covering the substrate; vias which are provided on the substrate so as to project from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate; an external wiring pattern which is provided on the protective layer, the external wiring pattern being connected to the vias; projection electrodes which are provided on the external wiring pattern, the projection electrodes being connected to the external wiring pattern to establish connections between the projection electrodes and the electronic circuit terminals, the projection electrodes having a predetermined height above the external wiring pattern; and an enclosure layer of a resin material which is provided on the protective layer, the enclosure layer covering sides of the projection electrodes and external surfaces of the external wiring pattern.
The semiconductor device of the preferred embodiment does not require the pads provided in the conventional CSP semiconductor device. In the semiconductor device of the preferred embodiment, the projection electrodes are connected to the external wiring pattern to establish connections between the projection electrodes and the electronic circuit terminals. The external wiring pattern connects the vias and the projection electrodes by the shortest distance. The semiconductor device of the present invention is effective in achieving downsizing of the semiconductor device as well as increasing the packaging density of transistors on the semiconductor device. As the connections between the projection electrodes and the electronic circuit terminals can be made by the shortest distance, the semiconductor device of the preferred embodiment is effective in maintaining the electrical performance of the connections at an appropriate level.
In another preferred embodiment of the semiconductor device of the invention, a semiconductor device includes: a semiconductor substrate; an electronic circuit which is provided in the substrate, the electronic circuit having terminals; an internal wiring pattern which is provided in the substrate, the internal wiring pattern being connected to the electronic circuit terminals; a protective layer provided on the substrate, the protective layer covering the substrate; vias which are provided on the substrate and projecting from the protective layer, the vias being connected to the internal wiring pattern at arbitrary positions on the substrate; an external wiring pattern which is provided on the protective layer, the external wiring pattern being connected to the vias; lead wires which are connected to the external wiring pattern, the lead wires being supported by a tape; and an enclosure layer of a resin material which is provided on the protective layer, the enclosure layer covering portions of the lead wires and external surfaces of the external wiring
Fukasawa Norio
Hamanaka Yuzo
Hozumi Takashi
Kawahara Toshimi
Matsuki Hirohisa
Armstrong Westerman & Hattori, LLP
Cruz Lourdes
Fujitsu Limited
Jackson, Jr. Jerome
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