Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2007-07-12
2009-12-01
Zarneke, David A (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE23011
Reexamination Certificate
active
07626271
ABSTRACT:
A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-distribution wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.
REFERENCES:
patent: 6166441 (2000-12-01), Geryk
patent: 6982494 (2006-01-01), Anzai, Noritaka
patent: 2004-006486 (2004-01-01), None
patent: 2005-064473 (2005-03-01), None
Kubotera & Associates LLC
Oki Semiconductor Co., Ltd.
Wagner Jenny L
Zarneke David A
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