Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-27
2003-08-19
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S301000, C438S588000, C438S652000, C438S654000, C438S660000, C438S663000
Reexamination Certificate
active
06607979
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a conductive film implementing, e.g., a gate electrode included in a MOS (Metal Oxide Semiconductor) transistor or an interconnection or wiring, and a method of producing the same. More particularly, the present invention relates to a semiconductor device capable of lowering the resistance of a conductive film thereof and a method of producing the same.
In parallel with the trend toward high speed, highly integrated semiconductor devices, there is an increasing demand for a decrease in the size of electrodes included in semiconductor devices and the size of interconnections between the devices. However, a decrease in the size, particularly a width, of electrodes and that of interconnections bring about a problem that the resistance of electrodes and that of interconnections noticeably aggravate signal delay, voltage fall and other circuit factors. Particularly, a polysilicon layer conventionally used as an electrode or an interconnection and lowered in resistance by a dopant aggravates signal delay because polysilicon has relatively high resistivity. To solve this problem, there has been proposed to form a titanium, cobalt, tungsten or similar metal film having a high melting point on a polysilicon film. Metal having a high melting point and silicon react to form a metal silicide layer having a high melting point and thereby form a polycrystal line silicide structure. Even the polycrystal line silicide structure, however, cannot lower the resistivity of the metal silicide having a high melting point beyond a certain limit. Specifically, when an interconnection or wiring is 0.2 &mgr;m thick or less and is reduced in width from conventional 0.18 &mgr;m to 0.13 &mgr;m, resistance lower than 4 &OHgr;.cm
2
is required as the sheet resistance of the interconnection. Such a low resistance is, however, difficult to achieve with the polycrystalline silicide structure.
A metal/polysilicon structure in which a film of metal having a high melting point is formed on a polysilicon film is one of recent achievements in the semiconductors device art. The metal/polysilicon structure is expected to implement low resistance because a high melting point, metal silicide layer is absent. Specifically, after a film of tungsten or similar metal having a high melting point has been formed on a polysilicon film, a semiconductor device with, e.g., the tungsten film is annealed. For example, after a tungsten/polysilicon (W/Si) structure has been formed as the gate electrode of a MOS transistor, ions are implanted in a source and a drain region. This is followed by annealing for activation. Annealing, however, causes polysilicon and tungsten to react with each other and form tungsten silicide (WSi).
In light of the above, a barrier metal film implemented by a titanium nitride (TiN) film or similar metal nitride film may be formed between the polysilicon film and the tungsten film in order to suppress the reaction of polysilicon and tungsten, as also proposed in the past. However, it is difficult to lower the resistivity of the metal structure, i.e., W/TiN structure even with the barrier metal film. In this connection, we found by measurement that the resistivity of the tungsten film forming part of the W/TiN structure was about seven to eight times as high as the resistivity of bulk tungsten. This is presumably because the crystal structure of the barrier metal film affects the crystallization of the overlying tungsten film and thereby suppresses the crystal growth of the tungsten film, limiting the decrease in the resistivity of the W/TiN structure.
To implement low resistivity, Japanese Patent Laid-Open Publication No. 10-12869 (prior art 1 hereinafter) discloses a conductive film that is a laminate of a tungsten film, a TiN film, and a polysilicon film. In this structure, the TiN film, which serves as a barrier metal film, is caused to recrystallize so as to increase the grain size. This improves the crystallization of the tungsten film and thereby lowers resistance. Japanese Patent Laid-Open Publication No. 10-289885 (prior art 2 hereinafter) teaches a conductive film in the form of a high melting point metal/TiN/polysilicon laminate structure. This conductive film is characterized in that the barrier metal film is provided with a double-layer structure in order to improve the crystallization of the overlying, high melting point metal film for thereby lowering resistance.
However, the prior art 1 needs an additional step for the recrystallization of the barrier metal film while the prior art 2 needs an additional step for providing the barrier metal film with a double-layer structure. Such an additional step makes a production line sophisticated when combined with the essential steps of sequentially forming the consecutive layers of the conductive film. Moreover, the recrystallization and double-layer structure both increase the film thickness of the barrier metal and therefore the overall thickness of the conductive film. This obstructs the implementation of thin electrodes and thin interconnections that is necessary for scaling down semiconductor devices.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device capable of reducing the resistivity of its top metal film without resorting to a sophisticated production line or increasing the thickness of a barrier metal film.
In accordance with the present invention, in a semiconductor device, a conductive film formed on a semiconductor substrate for forming an electrode, an interconnection or the like is implemented as a laminate of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point, as named from the bottom to the top of the laminate.
Also, in accordance with the present invention, a method of producing a conductive film included in a semiconductor device includes the steps of sequentially forming a laminate made up of a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on an insulation film in this order, and annealing the laminate to thereby lower the resistance of the metal nitride film.
Further, in accordance with the present invention, a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride layer having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, patterning the conductive film to thereby form the gate electrode, implanting ions in a source and a drain region in a semiconductor layer by using the gate electrode as a mask, and effecting annealing to thereby activate the resulting ion implanted layers and lower the resistance of the metal nitride film at the same time.
Moreover, in accordance with the present invention, a method of producing a gate electrode included in a MOS transistor includes the steps of sequentially forming a polysilicon film, a barrier metal film and a metal nitride film having a high melting point on a gate insulation film in this order to thereby constitute a conductive film having a laminate structure, annealing the conductive film to thereby lower the resistance of the metal nitride layer, and patterning the conductive film to thereby form the gate electrode.
REFERENCES:
patent: 5652181 (1997-07-01), Thakur
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 5861340 (1999-01-01), Bai et al.
patent: 5877074 (1999-03-01), Jeng et al.
patent: 5888588 (1999-03-01), Nagabushnam et al.
patent: 5907188 (1999-05-01), Nakajima et al.
patent: 5923999 (1999-07-01), Balasubramanyam et al.
patent: 5960303 (1999-09-01), Hill
patent: 6004869 (1999-12-01), Hu
patent: 6087700 (2000-07-01), Fazan et al.
patent: 6103609 (2000-08-01), Lee et al.
patent: 6146742 (2000-11-01), Hsieh et al.
patent: 6187656 (2001-02-01), Lu et al.
patent: 6198144 (2001-03-01), Pan et al.
patent: 6207568 (2001-03-01), Liu et al.
pate
Everhart Caridad
Luu Chuong A
NEC Corporation
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